a bit unusual logic

was mentioned in pre-prev. post - now i finalized the testing of it - not that it´s ok to go but i just run out the ideas how to futher adjust it . . .

the idea as usual for 1.2V (single battery fed) logic is to make it work at all discharge levels of the battery (1.68V) 1.46V . . . 1.1V(0.75V) -- in common after the battery is discharged below 1.13V it´s power output is limited 4mA continuous drain (10 to 20mA peak loads) and it´s getting worse in minutes - for rechargeable Ni-MH-s the critical voltage is likely lower - that is - they preserve their power output below 1V (unloaded) terminal voltages

 the 1-st run ::


??? still oscillates at 240mV supply ???

Correction: to drop X0 faster usually takes to decrease RC and/or to increase RB

and the 2-nd run ::


tested(read: simulated) at 600mV where the oscillation signal still crosses the threshold
it has 760mV zener that means the supply should be above that level

"XC-trigger" versus JK-trigger - the more idiot proof v. of which is a "pulse-counter" - a pulse-RS-trigger based T rigger
the question here might be  that why to go so complex when the 2-transistor 2-resistor + number of inputs count of diodes do the trick as well . . .
. . . it is that - due the differences in real components - the signal continuity may be lost using simple design
+ the above designs "eat" better the supply and input signal range variations - making it more realistic that i might do something with old SMD transistors "saved" from old blown devices . . .

[Eop]

Custom Low Voltage Zener Benchmark

items of interest I_ON stability :

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Fri, 05 Feb 2016 16:56:00 GMT -- Update! ← the ↑ graph plots the zeners´ terminal voltages against master supply current !!! . . . so here a bit more definitive v. :

where the Max. states the frequency @ which there still is no obvious hysteresis present (as for V_EXT rising/falling "forces" difference in V_ZNR) AND the Nrm. states the frequency @ which there still is no peak overshot @ the leading edge (a feature that is present in many commercial voltage regulators and references !!!)

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and the winner is Z3 :

followed by:

[Eop]

Errors induce new knowledge

basically - i was after a while testing a new DTL concept - it was quite a long while - so i didn't exactly recall the threshold test circuit - and due the specific nature of this new DTL the wrong 3-shold circuit started to oscillate ►► reproduced on ancient SN7400

it´s component level model is not the exact thing - but quite close
+ notice the osc. startup forcing . . .

. . . damn i re-opened this post on editor and it there displays correct - here it --

<span style="border-color: red; border-style: solid; border-width: 0 0 1 0;">startup forcing</span>

-- does NOT ????? (?blogger . . . bullsh¡t! -- they have no error here -- it´s someone´s work undone (low budget . . . whatever they don´t have . . .))

+ the RIGHT layout

[Eop]

Op.-Amp. Tutorial No.1 - DC Level Shift

Buffered v. . . .

a level sift with and without the polarity inversion

. . . Unbuffered

You dont want to level-shift the unbuffered signal !!!

[Eop]