Comparing TTL JK Triggers' Logic Designs

There was recently needed a realistic JK Simulation for which i had to set up one coz the Spice has no built in version . . . so i compared the equivalent circuits at d/s-s and made few additional 1-s.

It turned out that at high speed some perform more accurate than the others

From d/s - the only good one was 74LS73 , from custom 1-s - 2 became out credible : a mod of '7474 into JK --and-- a "self-confirming" JK -- that was made to have a least error JK to compare others against . . .


In the moderate/high speeds all perform correct

The variations occur near the speed limit

+ The last two compared ...

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High Noise Immunity Logic - Update 2

When you go round and round improving the circuit you may forget to keep track on some relevant parameters . . . such as the Threshold Voltage and the very Noise Immunity . . . while i improved the speed and the supply range

so - i had to make a new zenerless central threshold variant with reduced speed A5►Q5 below
/// the problem with V_TH being near the one of the rails is that if the rail is noisy it may interfere with low/high threshold level , then again - when the V_TH is near the center the logic may "hang in the middle" or wave around it . . . randomly -- but near the center is more secure from the rail noise

thus - it would be wise to increase the hysteresis . . . but also this has..

• ..a disadvantage in "wave"/signal propagation speed -- as each gate has to complete the hysteresis size transition before the information propagates;
  it must be tested by practice  and decided (oriented to the target application) how much is optimal --or-- least error prone --or-- other
• ..a disadvantage as it adds up to required component count , budget , build time/-space ...

a Falstad Simulation of the oscillator suggests the lower voltage limit to use for OSC. is about 3.5V ? or below → a modified oscillator ← requires a kick start (a RESET in Falstad)

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