This ?? textbook fig. appears to be too common
and misleading
while it's likely used as below
there's no need for comparator per bit if it's (+) INP is connected to somewhere below 1.4V in this example ((this is how you tune such a sh¡t with spice . . . all fun!)) -- shortly put you write your bit by setting global S and Z(S̅) while C (EW) E (ER) W (R/W̅) are on their respective LOW level , then enable write by pulling C (of a specific memory cell) to it's HIGH level and after setting time back to LOW -- you read a bit by enabling read (disabling input) by pulling global W HIGH cell specific E HIGH (which requires a 3-rd transistors to be added to both shoulders of this RAM cell (see fig. below) and enabling a level drop dn ((by pulling (((this rebuilt))) E HIGH)) to a global OUTPUT BUS) that sets the MR which in turn is fixed at output register as D0 (for example)
Yes thank you Google's Einsteins for removing my unicode overlines , thank you ((mõned inimesed on ikka sündind idioodid))
since using PNP read-gate it seems the 3-rd transistors're not required
while it's likely used as below
there's no need for comparator per bit if it's (+) INP is connected to somewhere below 1.4V in this example ((this is how you tune such a sh¡t with spice . . . all fun!)) -- shortly put you write your bit by setting global S and Z(S̅) while C (EW) E (ER) W (R/W̅) are on their respective LOW level , then enable write by pulling C (of a specific memory cell) to it's HIGH level and after setting time back to LOW -- you read a bit by enabling read (disabling input) by pulling global W HIGH cell specific E HIGH (which requires a 3-rd transistors to be added to both shoulders of this RAM cell (see fig. below) and enabling a level drop dn ((by pulling (((this rebuilt))) E HIGH)) to a global OUTPUT BUS) that sets the MR which in turn is fixed at output register as D0 (for example)
Yes thank you Google's Einsteins for removing my unicode overlines , thank you ((mõned inimesed on ikka sündind idioodid))
since using PNP read-gate it seems the 3-rd transistors're not required
the plot is basically same than above
-- A , B for monitoring mem-cell's state
-- S , Z set global data
-- SB , ZB , W are respectively D , NOT D , NOT write (they can be global and then we still need a 3-rd tansistors for data read)
-- SB , ZB , E are respectively D , NOT D , NOT read (mem-cell specific)
-- SR , ZR , MR are respectively D , NOT D , D read (all global ((to max number of bits that can be reliably set and read also limited by power consumption (((e.g. the memory block can be suspended to low-power mode - still preserving it's data - while no read write to that area occurs))) )) )
re: about Google's Einsteins -- it appears that when pasting unicode overline to Blogger Editor it shows there - but when you save/publish and then reopen for modification - the unicode overlines won't display in Compose nor HTML view (however they're preserved and after re-save they'll show up in www blog) -- so now i have unicode overlines and CSS ones -- thanks for Google's Einsteins -- who newer take their job seriously (or perhaps someones pet pig programmed the Blogger Editor -- in which case it's to be considered as an achievement !!!)
back to 3+3 transistor (separate RW) RAM
The interesting part of this circus is thus over. It seems the W pin has no much effect (at least with this 2-bit v.) -- it might be reducing errors near max fq. op. . . . perhaps. So the conceptual part is over - the rest is fine tuning and right component + layout selection/dev. . This one is over 1000x slower and inefficient than the commercial FET memories -- the background of this circus is that at the time i attempted to make it run all under 1.2V and it didn't quite work out -- so now "we" used some more realistic voltage levels . . . (end, over & out ×·
[Eop]
re: about Google's Einsteins -- it appears that when pasting unicode overline to Blogger Editor it shows there - but when you save/publish and then reopen for modification - the unicode overlines won't display in Compose nor HTML view (however they're preserved and after re-save they'll show up in www blog) -- so now i have unicode overlines and CSS ones -- thanks for Google's Einsteins -- who newer take their job seriously (or perhaps someones pet pig programmed the Blogger Editor -- in which case it's to be considered as an achievement !!!)
back to 3+3 transistor (separate RW) RAM
The interesting part of this circus is thus over. It seems the W pin has no much effect (at least with this 2-bit v.) -- it might be reducing errors near max fq. op. . . . perhaps. So the conceptual part is over - the rest is fine tuning and right component + layout selection/dev. . This one is over 1000x slower and inefficient than the commercial FET memories -- the background of this circus is that at the time i attempted to make it run all under 1.2V and it didn't quite work out -- so now "we" used some more realistic voltage levels . . . (end, over & out ×·
[Eop]