Synchronours Double Quadrature Osc.

Notice the difference in the bottom inverters' biasing

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v.2 :: Lo-Frequency

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[Eop]

inverter demystified

there're some weird schematics up in the web as someone uses a transformer to input 12V squarewave and it outputs 153V one ?? -- i yet haven't figured out a transformer parameters for this trick

here's some tests that do simulate at least in more realistic -- as i see it ?

a sine test ::

a square wave test ::

is basically DC/DC -- with what to use for alternating the OUTP = don,t care -- a "programmed" resistors in this case

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[Eop]

another 1.2V DTL variant

trivial random inverter osc. test

2N2222 OUTP , a composite "diode" from 2N2907 1N4148 -- NAND logic
designed for up to 1...2 MHz operation at 1.2V supply
at lesser speeds it can work starting from 620mV supply ...
... which has much no point in practice coz below ??? say 850mV (good battery types) usually 1.13V (most battery types) the terminal voltage drops fast (some minutes even seconds -- tough -- during that some startup circuits can be driven) and deceases -- so below 1.13V (unloaded) terminal voltage the 1.2V battery is basically empty

counters compared XC , JK , Pulse , T

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[Eop]

component level model for C-MOS inverter

Revised the R.DS.ON data for C-MOS inverters

thought to complete the set by scanning the threshold levels
1-st came out with an over complicated setup -- that however worked fine at least for 3-shold meter circuit

analysing the problem revealed the alternate more simple 3-shld. metering possibilities -- however i can't tell witch of those is more reliable - as by simply measuring the current through opening FET gives us lower 3-shld. points than any of these metering grids . . .

so shit - started from the middle using approximate initial values and tuned the CLM (component level model) on a run . . .

i had previously done some measurements that suited the purpose - of tuning the CLM

the apx. src. fn. for the prev. graphs

! note that the SPICE uses "randomly" RAD-s and DEG-s (as why to make life easier by using phs. std. radians -- as it is a scientific application ? - perhaps another computer game ....)

the ↓next↓ is how we got to ↑above↑

confirming/testing/simulating a threshold metering variant

it seems i should have made the NOT gate to use more power (to be faster) -- &shit -- it'll do for testing as low speed MOS inverter -- so here some test follow :
at your Left -- 5x ring osc. has !usually! enough  delay for digital levels to settle e.g. 5x ring osc. generates "square" trapezoid wave while 3x ring osc. does sine or triangle
at your Right -- a "std." digital R-C CLK circuit

at your Left -- synchronizing 5x & 7x ring osc.-s
at your Right -- setting up something resembling to a quadrature osc.

at your Left -- the same "quadrature osc." at lower speed
at your Right -- . . . as the RA is less than RB -- then here we reference the inverter to a digital threshold point and feeding the output of the inverter to inverting threshold reference . . . after "optimizing" this type of oscillator we got the schematic shown on the fig.

at your Left -- some oscillator i came up with before starting to use the Spice simulator (. . . "what's it worth")
at your Right -- another variant of something i used with experimental DTL gates

at your Left -- an experimental X-tal driver -- when it stabilizes there is still some effect from a near square wave output . . . which is not good . . . i assume
at your Right -- more simple v. of an experimental X-tal driver has even worse sq.wave mix-in -- there must be some sort of dynamic attenuation of the feedback as the crystal charges up (at too strong fixed attenuation the crystal won't likely start up at all . . .)

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[Eop]

concept design of the switching dc voltage inverter

it seems the fast comparators are the soul of the whole thing - replaced the fast op amps coz they failed at various cases

uses 2N3906 2N3904 2N7002 BSS84 - not especially optimized or tuned for anything specific - no real life testing ... !
[Eop]

Custom eXperimental 0.6 ... 1.6 V inverter

From back to forth --

32k768 Qz Driver ::

the interesting thing about this X-tal pusher is that the 1 single inverter most likely has a sufficient gain and speed to manage the task (if it's already oscillating) but using uneven no. of gates (1,3 were tested) and increasing the +feedback the oscillations start ubruptly at 100x to 300x higher fq. than the one of the quartz -- otherwise the quartz won't get into phase lock with feedback and thus won't collect the energy for start up ???
-- however the shown - an even no. of gates - v. has quite flexible tuning range where everywhere the oscillations do start e.g. the quartz gets phase locked with feedback and starts storing the energy . . . this is the first time i encounter such . . . curious ?

AA(AAA) behavior/capabilities ::

. . . simple things are complex to design ::

[Eop]

inverter test concept2 types of pulse generators1W chaos from fixed +5V

--- shortly -- i built an intuitive transformer to test the solar battery charger design . . . then i attempted to figure out how to drive it somewhat reasonably ---- the op.-g range for following is unknown ---- not speaking of special design for hi current high fq. pulse transformers F;X F;X F;X

the pulse generators are required everywhere not only solar-battery inverters ... so i revisited an old concept

. . . and figured out sort of a complementary v. for it
v. (A)

v. (B)

. . . and a chaos generator - though quite efficient by simulation
v. (C)

[EoP]

1.2V inverter again

The goal :: is to define / design a low power logic for abstract use in powering by "empty" 1.2V batteries

In common the loaded 1.2÷1.5V battery keeps it's terminal voltage above 1.0V , internal resistance - fresh ... "empty" 250÷500mΩ ... 750÷1250mΩ (varies more by battery type and less by manufacturer -- should be measured for specific application)

If the internal resistance goes beyond "1250"mΩ (very apx. value for critical Lim.) it starts rising fast and also the battery's unloaded terminal voltage starts to drop significantly dn2 0.9÷0.8V (◄ below that the battery can be used as - say a 1 minute - to load the capacitor to 550÷770mV and then switch that charge somewhere)

So the secondary use for batteries can be the "central" "dropping voltage" mode - unloaded terminal voltage 1.13 ... 1.0 V output current 20 ... 1mA - thus - the supplied power 23 ... 1.0 mW . . . so if you "define" a mW application such can still work several hours

Back to inverter - the graphs. ::



about ::

• The simulation is verified for 0.9 to 1.9V to be operating as expected
• It is normal to expect for the fast counters not to go over the 1-10th of their simulation frequency
• It is also normal to expect they wont go at any frequency (coz the collector resistance , output load capacity , other ...)
• ... otherwise it'll draw some 14µW at 1.2V U_CC - in other words - ! 1mW supply can push 1000 : 14 = 71 inverters OR 35 RS-triggers (/ D-triggers) OR 12 C-triggers (a 12 stage counter/divider) ►►
• ►► since you have to select the similar-ß BJT-s and to tune 3-shold for each inverter - then - it's impractical to build anything based on components that inverter's TEST prototype here has

▲▲ the entire bullsh¡t is required to pre-calibrate my system before an attenpt to do something with something₂ called "Electric VLSI Design System" -- so as i proceed in an unusual way - the 'log 's provided in case any sub-grid of this insanity 'd B a pt. of interest . . . 3,2,1,OFF

1.2V experiment

This shit has survived the output short circuits for so far // the lucky idiot stands for clear current path through PN junctions to ground /!\ the LT Spice seems to overlook such condition !!! and simulates "fine" - as if there were large resistance in series with PN junctions ??? - so you have to pay extra attention your currents will take the realistic values ...

otherwise it's quite stable (* the 11-th v. of this particular) 1.2V supply (i have no scope so you'd like to check it for possible noise) drawing some 6mA - which i find too excessive for 6LF22 so i likely'll convert something out of these for replacement - if they run even close to what they simulate(*) ◄ this one is a design concept and likely has inacceptable dependency both on load and on supply

... so much for supplies - thanks to "1-st" i was able to check the "performance" of the various "discreet" logic inverter concepts ...

and some more (this bullshit editor is really great) i like the 3-transistor 1-s (( but it's tricky to get them generating the Sq.Wv at that current mode // + it'd take a lot of components (to test verify and threshold match e.c. , e.c. ) to get - say - slow A/D converter built from )) - the next comes is 2D+2R base-shunt MP42 v. but it also doesn't want to oscillate too well - the last 1 (the lowermost in the last graph) has only 1 stage built - so i donno about it yet (perhaps i should yet rise it's threshold level before testing the Sq.Wv generator -- otherwise the varying ß may cause problems ... )

/// the graphs are normalized to all meters' average - V.max " = V.supply ' = 1.2V ' " - during the measurement - so they contain systematic errors - depending of the set of multi-meters used (likely is the same for the same "type" of inverter)