Had 2 modify smth. i call XC trigger

the test (Update @ MMXVI-02-11 to compare with TTL (SN74xx))

the DTL here is other than in prev. post	X-C 3-ger v. P counter (TTL)
the latches tested	X-C 3-ger (TTL)
L→R , U→D -- pulse-counter , JK-trigger , D-trigger , XC-trigger <•> the pulse-counter uses the pulse-RS-trigger which locks it´s INP and OUTP during transition <•> the XC-trigger uses an adittional state buffer to gain better speed	. . . it seems so far the XC-trigger performs the best of it's kind , if it's implemented correct ??

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about Blogger editor :: using the <dir> tag blunts the editor (in a Compose view) -- it can´t add lines [Shift]+[Enter] correctly -- nor to style text e.g. [Ctrl]-[B] has no effect inside <dir> in Compose view

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[Eop]

Errors induce new knowledge

basically - i was after a while testing a new DTL concept - it was quite a long while - so i didn't exactly recall the threshold test circuit - and due the specific nature of this new DTL the wrong 3-shold circuit started to oscillate ►► reproduced on ancient SN7400

it´s component level model is not the exact thing - but quite close
+ notice the osc. startup forcing . . .

. . . damn i re-opened this post on editor and it there displays correct - here it --

<span style="border-color: red; border-style: solid; border-width: 0 0 1 0;">startup forcing</span>

-- does NOT ????? (?blogger . . . bullsh¡t! -- they have no error here -- it´s someone´s work undone (low budget . . . whatever they don´t have . . .))

+ the RIGHT layout

[Eop]

SN74xXX transistor level models

Tested the SN74xXX transistor level models + some features

( extends about :: http://chpsndtch.blogspot.com/2014/08/spice-alternate-for-sn7404-1551.html )

Testing all experimental variants

+ A RANDOM OSCILLATOR SETUP ::

what a waste of power for 50MHz ( actually it's for high "slew rate" for level transitions & "output replicate-ability" . . . anyway insane . . .)

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[EoP]