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Showing posts with label Discrete Logic. Show all posts
Showing posts with label Discrete Logic. Show all posts
Saturday, August 8, 2020
Saturday, November 23, 2019
Comparing TTL JK Triggers' Logic Designs
There was recently needed a realistic JK Simulation for which i had to set up one coz the Spice has no built in version . . . so i compared the equivalent circuits at d/s-s and made few additional 1-s.
It turned out that at high speed some perform more accurate than the others
From d/s - the only good one was 74LS73 , from custom 1-s - 2 became out credible : a mod of '7474 into JK --and-- a "self-confirming" JK -- that was made to have a least error JK to compare others against . . .
In the moderate/high speeds all perform correct
The variations occur near the speed limit
+ The last two compared ...
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It turned out that at high speed some perform more accurate than the others
From d/s - the only good one was 74LS73 , from custom 1-s - 2 became out credible : a mod of '7474 into JK --and-- a "self-confirming" JK -- that was made to have a least error JK to compare others against . . .
In the moderate/high speeds all perform correct
The variations occur near the speed limit
+ The last two compared ...
[Eop]
Sunday, November 17, 2019
High Noise Immunity Logic - Update 2
When you go round and round improving the circuit you may forget to keep track on some relevant parameters . . . such as the Threshold Voltage and the very Noise Immunity . . . while i improved the speed and the supply range
so - i had to make a new zenerless central threshold variant with reduced speed A5►Q5 below
/// the problem with VTH being near the one of the rails is that if the rail is noisy it may interfere with low/high threshold level , then again - when the VTH is near the center the logic may "hang in the middle" or wave around it . . . randomly -- but near the center is more secure from the rail noise
thus - it would be wise to increase the hysteresis . . . but also this has..
a Falstad Simulation of the oscillator suggests the lower voltage limit to use for OSC. is about 3.5V ? or below → a modified oscillator ← requires a kick start (a RESET in Falstad)
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so - i had to make a new zenerless central threshold variant with reduced speed A5►Q5 below
/// the problem with VTH being near the one of the rails is that if the rail is noisy it may interfere with low/high threshold level , then again - when the VTH is near the center the logic may "hang in the middle" or wave around it . . . randomly -- but near the center is more secure from the rail noise
thus - it would be wise to increase the hysteresis . . . but also this has..
- ..a disadvantage in "wave"/signal propagation speed -- as each gate has to complete the hysteresis size transition before the information propagates;
it must be tested by practice and decided (oriented to the target application) how much is optimal --or-- least error prone --or-- other - ..a disadvantage as it adds up to required component count , budget , build time/-space ...
a Falstad Simulation of the oscillator suggests the lower voltage limit to use for OSC. is about 3.5V ? or below → a modified oscillator ← requires a kick start (a RESET in Falstad)
[Eop]
Saturday, May 28, 2016
1.2V Logic revised
I re-tuned most of all of my 1.2V DTL logic designs to function at least in 0.9 to 1.7 V range (using the verification on the first figure of linked post) and run them under the same oscillator setup, updated the past stats. :
here're the most time efficient and energy efficient ones :
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the yellows are the old v.-s of some of the inverters before revision
here're the most time efficient and energy efficient ones :
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Wednesday, February 3, 2016
Had 2 modify smth. i call XC trigger
the test (Update @ MMXVI-02-11 to compare with TTL (SN74xx))
about Blogger editor :: using the <dir> tag blunts the editor (in a Compose view) -- it can´t add lines [Shift]+[Enter] correctly -- nor to style text e.g. [Ctrl]-[B] has no effect inside <dir> in Compose view
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the DTL here is other than in prev. post
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X-C 3-ger v. P counter (TTL)
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the latches tested
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X-C 3-ger (TTL)
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L→R , U→D -- pulse-counter , JK-trigger , D-trigger , XC-trigger <•> the pulse-counter uses the pulse-RS-trigger which locks it´s INP and OUTP during transition <•> the XC-trigger uses an adittional state buffer to gain better speed | . . . it seems so far the XC-trigger performs the best of it's kind , if it's implemented correct ?? |
about Blogger editor :: using the <dir> tag blunts the editor (in a Compose view) -- it can´t add lines [Shift]+[Enter] correctly -- nor to style text e.g. [Ctrl]-[B] has no effect inside <dir> in Compose view
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Thursday, June 26, 2014
Unverified
that the following would EXIST
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(waiting the 'logger & FF becoming responsive)
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while those booster diodes might do the trick - the design wont work on voluntary diodes - especially those labelled on figure coz the high ohmic collector load wont be enough in real life to lock the input diodes (or lock 'em fast) e.g. the inverters won't work at all or would work 10-s of times slower than the simulation does F;i yoo-hoo . . . everything may work better if you rise the feed voltage above ?? 1.85V 2.0V 2.16V or higher ?? (the dif.-amp starts working properly above-equal 9.6V . . .)
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(waiting the 'logger & FF becoming responsive)
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(still waiting)
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((◄◄restored apx. as it was))
while those booster diodes might do the trick - the design wont work on voluntary diodes - especially those labelled on figure coz the high ohmic collector load wont be enough in real life to lock the input diodes (or lock 'em fast) e.g. the inverters won't work at all or would work 10-s of times slower than the simulation does F;i yoo-hoo . . . everything may work better if you rise the feed voltage above ?? 1.85V 2.0V 2.16V or higher ?? (the dif.-amp starts working properly above-equal 9.6V . . .)
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Saturday, February 8, 2014
1.2V Discrete Logic Lab
Prj. thread history::
at this point i am likely able to design better of any type of these xTL stages however there are some things that came out in prev. studies::
1) the simple TTL NAND (up right) supports higer frequencies but only up to 3-4 input gates
2) the CMOS type gates (lowwer right) consist of "too many" components
3) the best power_draw : component_count : input_count : MHz_per_unit_Power is top left
Stats:
what is being marked here is exceptional to studied set designs - lets take a closer look:
is the highest frequency v. of the exceptions a TTL stage based on 2N5087 (good sensitivity at low power) as the exceptional performance is due to the performance of that transistor drawing in average 130µA/stg.
the 2-nd fast exception being tested for XOR3 against XOR3=fnOf(XOR2) , it's NAND gate:
again we have the 2N5087 - used inplace of russian МП42Б germanium 1 - based design drawing in average 9µA/stg.
and the slowest exception drawing in average 1.87µA/stg.
the 2N5087 based
the primary objective of this research was to find optimum way to utilize some old transistors as misc. LE 1.2V logic gates
we made some findings on this subj. but it still remains far from being researched
at this point i am likely able to design better of any type of these xTL stages however there are some things that came out in prev. studies::
1) the simple TTL NAND (up right) supports higer frequencies but only up to 3-4 input gates
2) the CMOS type gates (lowwer right) consist of "too many" components
3) the best power_draw : component_count : input_count : MHz_per_unit_Power is top left
Stats:
what is being marked here is exceptional to studied set designs - lets take a closer look:
is the highest frequency v. of the exceptions a TTL stage based on 2N5087 (good sensitivity at low power) as the exceptional performance is due to the performance of that transistor drawing in average 130µA/stg.
the 2-nd fast exception being tested for XOR3 against XOR3=fnOf(XOR2) , it's NAND gate:
again we have the 2N5087 - used inplace of russian МП42Б germanium 1 - based design drawing in average 9µA/stg.
and the slowest exception drawing in average 1.87µA/stg.
the 2N5087 based
the primary objective of this research was to find optimum way to utilize some old transistors as misc. LE 1.2V logic gates
we made some findings on this subj. but it still remains far from being researched