Showing posts with label pulse-trigger. Show all posts
Showing posts with label pulse-trigger. Show all posts

Tuesday, August 8, 2017

Misc. "non-std." RS-triggers

derived from the idea of the pulse RS trigger (← the referred post has been updated (the "pRS trigger as ↓below↓ contains a bug !") )

ALL
BOXES (positioned as above)
 (blah, blah ....) . . . the upper plot on the graph (N,L) , lower right (X4) is the "first attempt" to "Pass Gate" model the function of the TTL v.´s substitute the upper right (X2) however it's actual function is - set the signal by first set input and update as soon as next clear input occurs (e.g. only one of the inputs being high) extra to that the first risen input locks the other one off so it has no effect as long the firsty stays high

. . . the lower plot on the graph (X,W) , upper right (X2) is what was the aim (similar to linked TTL´s substitute at the beginning of the post) -- the function - set the OUTP by the first risen INP , ignore all input until both inputs are pulled down

. . . the 2-nd lower plot is for "Pass Gate" v. of (X2) - the (K,M) graph , upper left (X1) - took a bit tricky "gate" drive logic to get it going the way it should -- the function - same as X2 only with a bit faster responce . . .

. . . the 2-nd upper plot (S,T) , lower left (X3) is as X2 and X1 only the OUTP is set when input is (Zero,Zero) and the output is set by the first risen from (Zero,Zero) - so the trigger here remembers where it should be going and goes there when INP is "clear" . . . (simple as soapy water)

• • •

the initial purpose of the kind of RS mod. was counters study as below (the N,L - X4 - v. won't work with the below v. of D-Latch coz it would continuously see it's inverted output and starts strobing while D-Latch passes data . . .)

+ an extreme v. of the above T-flops with an experimental Pass Gate



[Eop]

Saturday, January 28, 2017

another 1.2V DTL variant

trivial random inverter osc. test


2N2222 OUTP , a composite "diode" from 2N2907 1N4148 -- NAND logic
designed for up to 1...2 MHz operation at 1.2V supply
at lesser speeds it can work starting from 620mV supply ...
... which has much no point in practice coz below ??? say 850mV (good battery types) usually 1.13V (most battery types) the terminal voltage drops fast (some minutes even seconds -- tough -- during that some startup circuits can be driven) and deceases -- so below 1.13V (unloaded) terminal voltage the 1.2V battery is basically empty


counters compared XC , JK , Pulse , T




[Eop]

Tuesday, February 3, 2015

SN7400 RS to "Old style" T - trigger

minimal counter configuration experiment ::

?! it's even possible . . . in theory . . .

+MMXV-02-08 the pulse T-trigger speed test
- thought to run this test in real but . . . what's the point -- it'd take also to build/test/verify a 15M detection circuit - that'd be more complex than the one below . . .


notice the complexity differences in between above and below circuits -- the speed difference seems to be roughly 1:3 . . . such as does it weigh up to gain some more speed by this "investment" , becides pushing the chip to it's limits increases the likelihood for errors
! Update 2021.08.01 :

found an error in the above circuit , a repair as a   (at the input the XOR must be faster than the NAND-s or the NAND-s should be delayed to be slower for proper operation)

[Eop]