some BJT dependencies -- the simualation vs. the d/s

the ß by Ic (has a very poor matching)

the saturation region of the collector (has a better matching)

junction capacitance (a realistic matching)

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High Noise Immunity Logic - Update 2

When you go round and round improving the circuit you may forget to keep track on some relevant parameters . . . such as the Threshold Voltage and the very Noise Immunity . . . while i improved the speed and the supply range

so - i had to make a new zenerless central threshold variant with reduced speed A5►Q5 below
/// the problem with V_TH being near the one of the rails is that if the rail is noisy it may interfere with low/high threshold level , then again - when the V_TH is near the center the logic may "hang in the middle" or wave around it . . . randomly -- but near the center is more secure from the rail noise

thus - it would be wise to increase the hysteresis . . . but also this has..

• ..a disadvantage in "wave"/signal propagation speed -- as each gate has to complete the hysteresis size transition before the information propagates;
  it must be tested by practice  and decided (oriented to the target application) how much is optimal --or-- least error prone --or-- other
• ..a disadvantage as it adds up to required component count , budget , build time/-space ...

a Falstad Simulation of the oscillator suggests the lower voltage limit to use for OSC. is about 3.5V ? or below → a modified oscillator ← requires a kick start (a RESET in Falstad)

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the 2-nd compile of the "Low Power Pulse Generator"

trivial warm-up test

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a high power (an inefficient pulse generator)

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a low power (an efficient pulse generator)

. . . optimizing for wider range of R4

. . . optimizing for component count

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Determining a near to the exact HFE value

Not providing how did we got there -- the I_C I_E are best to be kept below-equal to the 1.5mA and less

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more ::

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utilities ::

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Bipolar Passgate Experiment

There are obviously more tests to be done to evaluate the thing . . . but so far there are 2 of them :

resistive load + sample and hold ::

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the Actual/Built LED verifier

as i was not about to build a PCB for this the sot-jFets were not used . . .

Spice design ::

Real build ::

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Comparing Constant Current Circuits (to sort/verify the LED-s with)

▼Fast/Simple/Robust/Trivial Op-Amp + BJT Setup▼
→ apx. 16mA ±30µA(0.2%)

[fig.1]

▼Complex/Trivial Op-Amp + BJT Setup▼
 → apx. 18mA ±24µA(0.1%)

[fig.2]

▼Simple/Experimental BJT Setup ( !? the Best ?! )▼
→ apx. 18mA ±60nA(0.0003%) 

[fig.3]

▼Full/Trivial BJT + N-jFet Setup ( also better than any op-amp variant ??? )▼
→ apx. 18mA ±300nA(0.002%) 

[fig.4]

▼Complex/Experimental Op-Amp + MOS-Fet Setup▼
(likely worse than it's BJT alternate -- the 2-nd ↑↑ fig. )
→ apx. 18mA ±120µA(0.7%) 

[fig.5]

▼Trying to get it right here▼
-- it seems that the op-amps should be fed from the separate supplies or otherwise the PSRR won't recover the precision reached at reference voltages
→ apx. 18mA ±48µA(0.3%) 

[fig.6]

((the work is in progress ...))

▼If you are stupid then knowing the right Op-Amp-s could save your day▼
(the node "SE" had the greatest error although the node "a0" has the least ??? -- about LT1012A)
→ apx. 18mA ±10µA(0.06%)

[fig.7]

-------- Update 2017.12.24 ::

▼a conditional opposite to "If you are stupid then knowing the right Op-Amp-s could save your day"▼

→ apx. 18mA ±7µA(0.04%)

 [fig.8.1]

a "Russian LM308" **

 [fig.8.2]

** it's nearest LT's substitute (so far)

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