CMOS Op Amp - simplified models

 arctan()/(π/2) versus tanh() ::

PS! :: this model was created for the fast retrieving of the effect and the response of the particular P-MOS input stage ... the output starts behaving weird near the rails !!!

which means the model cannot be used for conventional simulation purposes !!!

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! Update ::

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 the (simplified-inexact MCP601) model for conventional use (compared against the Ti-s LMV831) ::

? interestingly the Ti's model has a suspicious behaviour on the input exceeding the supply rails ???

? the P-Spice model of the LMV831 accounts the common mode range ending some 1V below the upper rail so it likely suits better the simulation that needs to take into account that limitation . . . my simplified MCP601 model is brought below ::

Listing of the : MCP601SM.cir ::

* Universal Op Amp * IN NI OUT Vss Vdd .SUBCKT MCP601SM 1 2 3 4 5 PARAMS: Rt=18 gms=1 nms=1 pms=.5 * USE C=30 PF IN MAIN CIRCUIT (CA TO CB). * INPUT R1 5 51 R=Rd R2 5 52 R=Rd M1 55 55 51 51 PcMfT m=pm M2 50 55 52 52 PcMfT m=pm C1 50 55 .2p M3 43 1 50 50 PcMfT m=pm M4 44 2 50 50 PcMfT m=pm M5 43 44 41 41 NcMfT m=nm M6 44 44 42 42 NcMfT m=nm R3 41 4 R=Rs R4 42 4 R=Rs I1 55 4 35u load * DIFFERENTIAL R6 8 17 100k B1 7 17 V=V(43,44) R7 7 17 10k C2 7 17 {srf} * MEDIAN / CLIPPER / Vcp B5 10 0 V=V(5,4)/2-vfz R5 10 0 10k * CP B3 8 0 V=(V(4)+V(5))/2 R8 8 0 10k * MED B11 8 13 V=V(10) B12 12 8 V=V(10) D1 6 12 SjD D2 13 6 SjD R11 11 6 1 * GAIN / SLEW L1 10 8 300n * V.med modified ! B4 10 11 I=(V(5,4)/2+vfz)*tanh(2**bm*V(7,17))/10k R10 11 8 10k C3 11 8 {srf} * OUTP B2 9 8 V=V(11,8) R9 9 8 R=10k C4 9 8 {srf} R12 9 3 R=30 .param gm={gms} .param nm={nms*gm} .param pm={pms*gm} .param Rd={Rt*2/6} .param Rs={Rt-Rd} * .param bm=13.25 .param bm=6.223 .param vfz=0.45 .param srf={0.23n/2} .MODEL NcMfT NMOS(L=2u W=42u KP=35u LEVEL=1) .MODEL PcMfT PMOS(L=2u W=84u KP=7u LEVEL=1) .MODEL SjD D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon) .ENDS

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[EoP]

CD4013 by state machine

 about

model

* CD4013S.cir * Q iQ CPE R D S Vss Vdd .subckt CD4013S 1 2 3 4 5 6 7 14 .param zVt = 2/(5**.5+3) .param zVtH = zVt/5 * OUTPUT 1Ohm R20 121 1 1 R21 122 2 1 S1 14 121 114 0 FMSW S2 121 7 114 0 FMiS S3 14 122 115 0 FMSW S4 122 7 115 0 FMiS * GENERAL B1 99 0 V=V(15,7)*2 R1 99 0 10k B2 98 0 V=zVt R2 98 0 10k R3 14 15 5E5 R4 15 7 5E5 C4 15 7 5E-13 * C 103 * R 104 * D 105 * S 106 B3 103 0 V=if(V(99)>2,V(3,7)/V(99),0) B4 104 0 V=if(V(99)>2,V(4,7)/V(99),0) B5 105 0 V=if(V(99)>2,V(5,7)/V(99),0) B6 106 0 V=if(V(99)>2,V(6,7)/V(99),0) * ED EL iD D Q iQ R10 110 0 1k R11 111 0 1k R12 112 0 1k R13 113 0 1k R14 114 0 1k R15 115 0 1k * ED - enable data Q0 110 .machine .state sa0 0 .state sa1 1 .rule sa1 sa0 (V(110)>V(98)) & (V(103)>V(98)) & (V(111)<V(98)) .rule sa0 sa1 (V(110)<V(98)) & (V(103)<V(98)) & (V(111)<V(98)) .output (110) state .endmachine * EL - enable latch Q1 111 .machine .state sb0 0 .state sb1 1 .rule sb1 sb0 (V(111)>V(98)) & (V(110)<V(98)) & (V(103)<V(98)) .rule sb0 sb1 (V(111)<V(98)) & (V(110)<V(98)) & (V(103)>V(98)) .output (111) state .endmachine * INP Buff iD _Q2 112 .machine .state sc0 0 .state sc1 1 .rule sc1 sc0 (V(112)>V(98)) & (V(104)<V(98)) & ( ( (V(110)>V(98)) & (V(105)>V(98)) ) | ( (V(110)<V(98)) & (V(113)>V(98)) ) ) .rule sc0 sc1 (V(112)<V(98)) & ( ( (V(110)>V(98)) & (V(105)<V(98)) ) | (V(104)>V(98)) ) .output (112) state .endmachine * INP Buff D Q2 113 .machine .state so0 0 .state so1 1 .rule so1 so0 (V(113)>V(98)) & (V(112)>V(98)) & (V(106)<V(98)) .rule so0 so1 (V(113)<V(98)) & ( (V(112)<V(98)) | (V(106)>V(98)) ) .output (113) state .endmachine * OUTP Buff Q Q3 114 .machine .state sd0 0 .state sd1 1 .rule sd1 sd0 (V(114)>V(98)) & (V(106)<V(98)) & ( ( (V(111)>V(98)) & (V(112)>V(98)) ) | ( (V(111)<V(98)) & (V(115)>V(98)) ) ) .rule sd0 sd1 (V(114)<V(98)) & ( ( (V(111)>V(98)) & (V(112)<V(98)) ) | (V(106)>V(98)) ) .output (114) state .endmachine * OUTP Buff iQ _Q3 115 .machine .state sx0 0 .state sx1 1 .rule sx1 sx0 (V(115)>V(98)) & (V(114)>V(98)) & (V(104)<V(98)) .rule sx0 sx1 (V(115)<V(98)) & ( (V(114)<V(98)) | (V(104)>V(98)) ) .output (115) state .endmachine .model FMSW SW(Ron=1 Roff=.1G Vt={zVt} Vh={-zVtH} Ilimit=.1) .model FMiS SW(Ron=.1G Roff=1 Vt={zVt} Vh={-zVtH} Ilimit=.1) .ends

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[Eop]

More experimental spice models

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Digital (SN7400 , SN7404 , SN7414 , SN7474 , SN7486 , SN74112)

how and when i use ↑these↑ :: is to determine the apx. dynamic power draw , relative I/O states , etc.

it is not advised to use these in complex digital simulations coz such takes excessive time ... and serves no conceptual purpose

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TLC555 (Ti's P-Spice , + a Less simplified , + a More simplified)

since my first Ti's TLC variant model conversion for the LTSpice got destroyed  in OS reinstall - i haven't had time to recreate it . . . so -- the simplified /!\ ideal /!\ models are "close enough" to run a principial simulations -- one must address the shortcomings of such . . . + moreover the ideal models lack some required damping and referencing internal components ← means: the simulation may hang due the shortcomings from such = all pins must be connected or referenced through R or R C networks ← the values of which may be crucial to simulation "stability" (not to hang , etc. ...)

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"DIGITAL" PASS GATE (not fully verified but so far a will do v. -- with 2 simulation examples)
(related post : Comparing TTL JK Triggers' Logic Designs)

example use

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[Eop]

Some experimental (mostly CLM) models

► Analog ◄ about ::

the models are (behave) sometimes (at some circuits) better than the manufacturer provided ones . . . anyway they are the way slower -- so , using the multiples of them dramatically slows down the simulation . . . /!\  since the op amps basically act all the same  /!\ it is advised to use similar Is , Vs , GBW , SR or better LTSpice's "built in" substitutes in case the simulation speed matters

________________________________________________________________ misc. files _remove_temporary_files.bat Deletes unused simulation data files ~about_these_files.txt ↑← This File →↓ ________________________________________________________________ .cir models AD633.asy ad633.cir Analog AD633 P-Spice Model of the analog 4-quadrant multiplier AD633AN.asy AD633AN.cir Simplified AD633 macro model AZ431.asy AZ431.cir TL431 functional analog of the Programmable Shunting Voltage Reference/-Regulator LM311.asy LM311.cir Voltage Comparator LM324.asy LM324.cir Op-Amp LM393.asy LM393.cir Voltage Comparator LT1011.asy ! built-in LTSpice built in model (at the default Path) of the Voltage Comparator (LM311) NE555.asy ! built-in LTSpice built in model (at the default Path) of the NE555 ________________________________________________________________ .asc subcircuit models AN6914.asc AN6914.asy LM393 component level functional anaolog of the OC OUTP voltage comparator K554CA3-A.asc K554CA3-A.asy LM311 component level functional anaolog of the OC-/OE OUTP voltage comparator KA7805.asc KA7805.asy CLM (component level "model" / functional anaolog) of the 3-terminal linear voltage regulator LM2903.asc LM2903.asy LM393 component level EXPERIMENTAL anaolog of the OC OUTP voltage comparator LM317T.asc LM317T.asy CLM of the 3-terminal linear voltage regulator LM324XI.asc LM324XI.asy CLM of the Op-Amp NE555ic.asc NE555ic.asy CLM KP1006BU1.asc KP1006BU1.asy CLM of the NE555 Kp140yg1208cx.asc Kp140yg1208cx.asy µA776 CLM Op-Amp (recommended at 15µA control current) KP140yg1408vA.asc KP140yg1408vA.asy LM308 CLM Op-Amp ________________________________________________________________ .asc circuit DEMO simulations NE555-TEST-Es1117-Plus.asc NE555-TEST-Es1117-Plus.plt NE555 - parameters TEST NE555-TEST-Es1117-Plus-A.asc NE555-TEST-Es1117-Plus-A.plt NE555 - parameters TEST 2 NE555-TEST-Es1117-Plus-B.asc NE555-TEST-Es1117-Plus-B.plt NE555 - parameters TEST 3 GCx93 - CLM - Test - Q104-mp.asc GCx93 - CLM - Test - Q104-mp.plt LM393 - test K554CA3 - CLM - Test - Q110-mp.asc K554CA3 - CLM - Test - Q110-mp.plt LM311 - OE test K554CA3 - CLM - Test - Q112-mp.asc K554CA3 - CLM - Test - Q112-mp.plt LM311 - OC test Random - Op-Amp - TEST - iZ-8aF-xF.asc Random - Op-Amp - TEST - iZ-8aF-xF.plt LM324(XI) CLM test ________________ ** [EOF]

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[Eop]

Verifying the MOSFETs´ RDS(ON)

. . . being used to BJT-s i always thought the R_DSON being some illustrative variable that has nothing to do with reality - amazingly enough the tests i performed verified it being NOT a theoretical figure !

used the MOSFETs (IRFZ44N and BUK455-60A) unmounted from cordless drills´ speed adjustment circuits

the IRFZ44N existed in Spice DB but for the BUK455-60A i used a model compilation method described in the [LT Spice Tutorial 6] website (which actually resulted in better match with reality this time ??)

 as for R_DS(ON)

as and for directly measured I_D, U_D, U_G

ah! - also modified in ↑that↑ spice tutorial the files RDSon test jig and Switching Time Test Jig coz they were totally impractical to use for given purpose (fine tuning your MOS-Fet models) respectively to Cust MosFETs - 01.asc and Cust MosFETs - 02.asc (note that you have partially pre-calculate and modify accordingly the component parameter values to get your response right)

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Update!

PS! Since the power supply (Mod.: SMP-100KB, Rev.: A3, Date Code: 8945, +12Vdc/3.75A - output) was not very stable (or depended on it´s ~AC input ???) the source data can be trusted from 1 to 3 digits (depending on conduction state of the FET and stability of the PSU) and contains extra to that the unknown systematic +other errors of the multi-meters -- this was not intended to be a precision measurement anyway - but for setting the apx. (static) device margins (near +25°C).

also there were used voluntary statistical alterations to guess better the values required to form a "believable" (?accepatable) output for R_DS .


[Eop]

Diode Д9К

a while ago i tried to add it's model to LT-spice - following the specs of common Spice diode model parameters' spec. - THIS didn't quite end up as expected ???

so now i just studied the response of the I(U) graph to random LT's diode model parameter change and came to smth. that in (near) static mode resembles to a real world Д9К

some process steps in graphical representation ::

? empty DIV ?? !Wow

!!"Q%%&&¤/(/ - jälle see "Googel" ei toimi (ma ei kujuta ette neid inimesi kes iga päev siia midagi toksivad , HELP! HELP!) . . . ok , mis kuradi pilt siin on ..
↑ the lab Z-Up - a bi-way scanning of the diode chain varying the curent ↑

↑ fresh 10x + old 1x graph + static I(U) dependency ↑

↑ .model D9K D(Is=40u Rs=.3 N=3.2 Cjo=12p M=1.2 tt=60n Iave=30m Vpk=30 mfg=SpiceCLOzE type=silicon) ↑
/!\use at your own risk/!\

xls's static I(U) dependency build/check plot

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? should i attempt to switch back to Compose view . . . (should backup this 2 note' B4) -- no switching! (not yet depressed coz the otherwise soo in-common Google malfunction) ('ll Save & FO here)

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[EOF]