i committed my std. linear regulator test only for 100x reduced time scale
the chip seems to survive an extended short circuit . . . at least virtually . . . and O'boy it passed that slow -- from where i wonder if it should be provided with external SC handling circuitry
the only negative thing about this was a realization that introducing the high capacitive load at it's output is something you don't want to do . . .
. . . which once again suggests using SMPS only prior to linear LDO as a pre-conditioner for , and states a requirement for dynamic - tracking and/or predictive - multi-mode -- multi-function power controller (( . . . which tracks the differential changes at it's output and selects the avail resources combined with (depending on) the dynamic state of the control circuitry to compensate or disconnect the output ASAP . . . such is easy to design for the narrow power range of the output , but more tricky for full possible one assuming optimization of the control power in accordance . . . ))
so whenever you won't be mounting cap.-s on the output near the name value of what's already there (the C3) this converter is more than a good . . . well - if it passes the repetitious SC test in real . . .
. . . otherwise it's possible to set up (a lot) more quiet supply (converter) with the SC and reactive loads handling you need -- especially for 100mA output -- that sounds much like a limit here . . .
get it right -- i see it as a very good chip -- only not forgetting that it's not an ideal one , nor suitable for every application !!!
[Eop]
