DC-DC LED-s Spice Experiment

No over-voltage protection ... no under-voltage lock-down ... no reverse polarity protection ... not built/tested in real life ... ::

555´s alternate ...

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The sensitivity test of some ideal diode circuits

... using the transistor model of the LM324 ... apx. down to 10% error

 

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Revised my LM321/358/324 transitor models

The best variant turned out to be (v.I) :

This v. is couple of times faster and with higher DC voltage gain than the actual LM324 , uses a different biasing circuitry and modified output stage . . . as it turned out it is difficult to get the ® d/s provided equivalent circuit to have the stability otherwise

. . . the 100Ω resistors seemed to improve the common mode rejection at the time they were added . . . however there has been modifications since -- at the moment there's no time to validate the effect for the final v. . . .

 some tests :

. . . compared to the second best variant (v.JI) and to the macro-model of the Op Amp in question . . .

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some audio power amp.-s

 src :: http://ludens.cl/Electron/audioamps/AudioAmps.html

. . . much likely the NE/SA/SE 5534 ( --or-- not using the additional neg. supply as shown below ) significantly limits the otherwise available output power ?! . . . the above circuit however is claimed to have rather decent linearity (not the output power) . . .

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▲ efficiency % 36.5% , P.OUT 370mW ▲

▼ efficiency : 27.6% , P.OUT 455mW ▼

Blah , blah , blah . . .

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Dedicated iC-s  ::

TAA300 / K174YH4 -- Left : Right -- 60.2% : 61.6% -- efficiency - power to 8Ω speaker (!! not to air)
P.OUT -- 810mW : 925mW

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KA2201 : efficiency 58.1% , P.OUT 1.66W

Blah , blah , blah . . .

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TDA2822 ::

!!! near ... realistic model : i set here the control current 3x of the one that results in near 6mA quiescent current -- that , in order to shift the upper bandwidth from below 10kHz to above the 20kHz ← which may not be the case for the real 2822 !!! -- efficiency 57.5% P.OUT 885mW

!!! simplified model : (likely behaves much better the real thing . . . + the supply range may be limitted at the low end !!!) -- (( !!! efficiency 87.3% !!! )) P.OUT 670mW

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Bootstrapped versus inverting op amp input impedance

about :

 

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Re : Pulse generators

 Previously : 2 types of pulse generators

well ... i re-designed the low power one (( i always re-design things from scratch to see where such ends up )) and it "minimized" to the prev. -- still a design relic invoked a new variant (( i "switched" the design in between the transistor and the op-amp/comparator based and mixed . . . so just wanted to test out the NPN only variant . . . ))

Note : both , but especially the right , are not too well tuned/biased (( i tested the pricipal/general functionality ))

+ a Linear Sawtooth with power stage (another same polarity transistors only circuit)

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Bandpass comparison

WYSIWYG ::

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Alternate for the BJT Flip-Flop

about :: the simple universal RS Flop has a deficiency -- "negative overshoot" at transistor bases . . . the quick fix would distort otherwise near perfect square wave ::

(the point here was to find an even charging/discharging capacitor based SW source not more complex the below Flop . . . since all such likely require fixed supply or much more complex circuitry the final option of TLV3691 or any substitute was selected)

. . . just checking the double T thingy for 50% duty clock source - but it appears to be requiring too strict tuning --and/or-- voltage source ::

Fortunately there exist a low voltage comparator (to cover that supply range ... otherwise any other SW source can be used) ::

+ a simple varying duty SW source test ::

and a better timed ones ::

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5-bit DAC

 Prev. follow up ::

 

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Poor Models of some Old Soviet Op-Amps + µA741

 

Name The closest analog К157УД2 2x LM301 К174УН4Б none К548УН1А LM381 co К553УД2 LM301 К554СА3 LM311 КР1407УД2 (LM4250) КР140УД1208 µA776C MC1776 КР140УД1408А LM308 КР140УД7 µA741 КР140УД8А µA740 (MC1556) КР538УН2 none КР538УН3А (LM387N co)

Name ss VSMIN ss VSMAX ss IS ss VIO ss IIO ss IIB ss RIDIF ss GBW ss SR ss

about ::

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Some tests :: Zipped Source

 

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Some more tests ::

 

PS ! the last figure specifies the INP voltage range ( ! not the the one of the OUTP ! )

. . .

an improved ver. of the above ::

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Virtual eval. of some LoVo OpAmp.-s

 is what the title says :

Text as a text :

Pass TEST *TLV314 -- struggles near rails but passes (1.8÷5.5V)* TLV2371 -- inp max 2.58V *TLV9102 -- struggles near the low rail but passes (2.7÷16V)* TL3472 -- inp min max 1.0 to 3.4 V OPA2990 -- inp max 2.49V *OP284 struggles near rails but passes better the TLV314 (3÷36V)* !!! -- MC33071 -- is over idealized model -- !!! (no significant problems) LMV824 -- inp MAX ? 3.1 to 3.8 V (exact value indeterminable) *LM7321 -- struggles near the rails but passes smoother than OP284 (2.5÷32V)* *LM6142 -- same as LM7321 but faster (1.8÷24V)* LM358 -- min max 404 to 2097 mV !!! a MACRO MODEL   ( the transistor model requires a scaled input to prevent the spurious oscillation !!! ) *AD8628 -- struggles near rails but passes somewhat worse the rest R2R passers (2.7÷5V)*

note : if there will be no spurious oscillations configuring the LM358 , LM324 as the unity buffer shown at above fig. then the sentence "the transistor model requires a scaled input to prevent the spurious oscillation" has no meaning in real-life otherwise the recommended biasing scheme is as http://tinyurl.com/yyvgyz32

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CD4013 by state machine

 about

model

* CD4013S.cir * Q iQ CPE R D S Vss Vdd .subckt CD4013S 1 2 3 4 5 6 7 14 .param zVt = 2/(5**.5+3) .param zVtH = zVt/5 * OUTPUT 1Ohm R20 121 1 1 R21 122 2 1 S1 14 121 114 0 FMSW S2 121 7 114 0 FMiS S3 14 122 115 0 FMSW S4 122 7 115 0 FMiS * GENERAL B1 99 0 V=V(15,7)*2 R1 99 0 10k B2 98 0 V=zVt R2 98 0 10k R3 14 15 5E5 R4 15 7 5E5 C4 15 7 5E-13 * C 103 * R 104 * D 105 * S 106 B3 103 0 V=if(V(99)>2,V(3,7)/V(99),0) B4 104 0 V=if(V(99)>2,V(4,7)/V(99),0) B5 105 0 V=if(V(99)>2,V(5,7)/V(99),0) B6 106 0 V=if(V(99)>2,V(6,7)/V(99),0) * ED EL iD D Q iQ R10 110 0 1k R11 111 0 1k R12 112 0 1k R13 113 0 1k R14 114 0 1k R15 115 0 1k * ED - enable data Q0 110 .machine .state sa0 0 .state sa1 1 .rule sa1 sa0 (V(110)>V(98)) & (V(103)>V(98)) & (V(111)<V(98)) .rule sa0 sa1 (V(110)<V(98)) & (V(103)<V(98)) & (V(111)<V(98)) .output (110) state .endmachine * EL - enable latch Q1 111 .machine .state sb0 0 .state sb1 1 .rule sb1 sb0 (V(111)>V(98)) & (V(110)<V(98)) & (V(103)<V(98)) .rule sb0 sb1 (V(111)<V(98)) & (V(110)<V(98)) & (V(103)>V(98)) .output (111) state .endmachine * INP Buff iD _Q2 112 .machine .state sc0 0 .state sc1 1 .rule sc1 sc0 (V(112)>V(98)) & (V(104)<V(98)) & ( ( (V(110)>V(98)) & (V(105)>V(98)) ) | ( (V(110)<V(98)) & (V(113)>V(98)) ) ) .rule sc0 sc1 (V(112)<V(98)) & ( ( (V(110)>V(98)) & (V(105)<V(98)) ) | (V(104)>V(98)) ) .output (112) state .endmachine * INP Buff D Q2 113 .machine .state so0 0 .state so1 1 .rule so1 so0 (V(113)>V(98)) & (V(112)>V(98)) & (V(106)<V(98)) .rule so0 so1 (V(113)<V(98)) & ( (V(112)<V(98)) | (V(106)>V(98)) ) .output (113) state .endmachine * OUTP Buff Q Q3 114 .machine .state sd0 0 .state sd1 1 .rule sd1 sd0 (V(114)>V(98)) & (V(106)<V(98)) & ( ( (V(111)>V(98)) & (V(112)>V(98)) ) | ( (V(111)<V(98)) & (V(115)>V(98)) ) ) .rule sd0 sd1 (V(114)<V(98)) & ( ( (V(111)>V(98)) & (V(112)<V(98)) ) | (V(106)>V(98)) ) .output (114) state .endmachine * OUTP Buff iQ _Q3 115 .machine .state sx0 0 .state sx1 1 .rule sx1 sx0 (V(115)>V(98)) & (V(114)>V(98)) & (V(104)<V(98)) .rule sx0 sx1 (V(115)<V(98)) & ( (V(114)<V(98)) | (V(104)>V(98)) ) .output (115) state .endmachine .model FMSW SW(Ron=1 Roff=.1G Vt={zVt} Vh={-zVtH} Ilimit=.1) .model FMiS SW(Ron=.1G Roff=1 Vt={zVt} Vh={-zVtH} Ilimit=.1) .ends

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LM311 & LM393 common mode sensitivity test

LM311 auto-biasing test

LM311 optimal (most sensitive) input voltage offset TEST

LM393 optimal (most sensitive) input voltage offset TEST

LM393 oscillator forcing the input to it's optimal common input voltage offset ... Vee/Vss/-Vs

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