►► custom SBS20 supply TEST+

as the previous design had quite high input voltage and i'm not into storing the loads of various capacitors @ my place - i banned the design ... chk,chk 4700µF 35V =? 1.6€ ↔ 1.3£ ↔ 2.2$ ↔ 7 MYR ↔ 17$HK -- i expected 2.5 / 2.6€ (perhaps i should go sopping XD) anyway the Prj. SUM ::

1. too high difference in between I/O Vtg.-s = not a good trend = too low efficiency
2. switching design = good efficiency at Hi / Full loads = mystery work to prevent / block  RFI
3. since it's an audio supply that should be ready already and i found a suitable I/O difference TF -- i stayed at linear reg. design below 50% efficiency ~210mV / -33dB output noise REAL v. -79dB SIMULATED ??? . . . anyway you can't hear the supply over the 'puter fans background noise

Step.2 ::

here you should be aware of the 2-simulation shortcomings a) the real current gains (at low currents) may appear significantly higher than those of simulated , b) the real current gains (at high currents) may appear significantly lower than those of simulated , +the temperature rise & frequency rise lower the ß & all BJT-s are not "Const.- ß" 1-s e.g I_CE rise AND/OR microbe hour I_CE lowers the ß , ++ the Hi-Fq. performance/-response of even the Hi-Fq. transistors may occur a lot worse of the 1 simulated

so - the Step.2 is a nice promise but if it fails after a week of testing it in REAL - we're still nowhere - so ::

Step.3 ::

the transformer stays below 40°C and LM337 pretty much the same at below-/ medium volumes , cooled with Fe heat-sink::

┌┐┌┐┌┐┌┐┌┐┌┐ ─┬  ┬─ ┌┬┬┬┬┬┬┬┬┬┬┬┐
││││││││││││  │  │  │││││││││││││
││││││││││││  │  │ ┌┤│││││││││││├┐
││││││││││││       └┤│││││││││││├┘
├┴┴┴┴┴┴┴┴┴┴┴┐ W  H  │││││││││││││
└┬┬┬┬┬┬┬┬┬┬┬┤       │││││││││││││
 ││││││││││││ │  │ ┌┤│││││││││││├┐
 ││││││││││││ │  │ └┤│││││││││││├┘
 ││││││││││││ │  │  │││││││││││││
 └┘└┘└┘└┘└┘└┘─┴  ┴─ └┴┴┴┴┴┴┴┴┴┴┴┘
│           │       │           │
├──── L ────┤       ├──── L ────┤

Fig.1

Dim.-s	20	29	27	LWH(mm)
	L(mm)	N(×1)	H(mm)	S(mm²)
	11	24	27	7128
	9.818182	6	27	1590.545
	20	1	27	540
	20	2	3.5	140
	3.5	2	27	189
* the edge length of the double sided sq.		2		9587.545	single- sided
		1		19175.09
LE2(cm)	9.791601	0.01	10	191.7509	S(cm²)
LE2(in)	3.854961	0.00155	25.4	29.72145	S(in²)
Mass		1.76	m(OZ)	50	m(g)

-- whitch might be not enough for prolonged full load op.

[EOF]

►► custom SBS20 supply TEST

funny enough even this won't satisfy the power draw by SBS20 at full volume about 2kHz SQ-wave input

previous test :: "230" (a TF name) :: 2.1W 11.7V 176mA (~AC parameters -- fuzzy >>)

(>> R_LOAD = 2·Z_TF2-ndary OR U_TERMINAL on R_LOAD = 11.7V I_RLOAD = 176mA P_RLOAD = 2.1W) )

THIS v. :: "NiMH18vdc" :: 6.3W 22.2V 284mA (not enough near full Vol.)

(what it came with) :: "SBS20" :: 1.2W 9.6V 129mA (◄ with built in (single) 1N4007 removed)

(-- so actually without it)

[EOF]

about Discrete Logic Simulation Specifics

(about: LT Spice analog signal simulation) sometimes adding a dummy LC resonator (AND/OR adjusting the "minimum timestep") improves the fine detail in simulation while sometimes it takes to kill all possible Hi-Fq. src. paths with large enough inductors to avoid "Timestep too small" errors ...

(+ some Discrete Logic Simulation Specifics) there seems to be a strong "INTEGER SYNCHRONICITY" - a programmatic synchronicity - in between the Digital grid and it's driving signals -- such as the fine adjustment of pulse timing parameters can give you drastically different simulation results -- it may occur also important to "RESET/initialize"(electronically) your circuit in very specific way for it to start and keep operating "/!\normally/!\" ◄◄ such is trivia in complex digital designs but here it gets extended with the INT SYNC. + unknown by me the LT-Spice specifics

some (random) Digital TEST-s

(the last is not 100% verified attempt of idiot-proofing the D-trigger)

custom SBS20 supply TEST

so as noted couple of posts ago the "thing" had not rectified ±5VAC transformer plugged to 9V.DC.IN (initially not my speakers - donno if "they" ever sold such sets F;i) -- after it sever'ly ended up it mal-design it became what seems to be a working instance at least it didn't exploded or anything in 1h test

teh TF (no'the ®) appears to be the "hottest word" here (over 42°C - i wonder if it's a problem , should be cooled , swapped to more powerful 1) . . . otherwise it's quite HUM3 witch the ~AC1 definitely wasn't

... quite a lot of  stuff to pack onto PCB-s & i donno about the thermal nor RFI design techniques - thus must include automated timeout- & therma-l switch-off-s - - - the relay - which me think is most reliable for such - uses apx. the power of the supply -- alternate would be motorized switch - that 'd need autonomous power or there should be more tests to verify  the design's secure enough to be left ON for ages

? ? ? ? i don't remember the ±5VAC had a fuse or anything (! usually the primary is protected with thermal fuse - usually ? not with double ...) - must read some stuff about from www ...

about the Z-up ::
Vtg.-2-bler ► voluntary filter ► supposedly 150mA current limiter (not fully tested) ► 16V voltage limiter ► 2-ry filter ► 9V regulator
-- note: some stuff may be prev. cfg.-s leftover and are not strictly requred by this v.
-- this v. may be not consistent at all possible modes e.g µ-blackouts , ~AC transients ... specific sound input to SBS20 . . . otherwise it seems to draw power LE to 50mA if the VOL is not set above apx 67%

[EoF]

DTL logic visualised

just wanted to see D-trigger in operation - is a 6 stage module - only made 2 so far - enough for the RS trigger

<iframe allowfullscreen="" frameborder="0" height="480" src="//www.youtube.com/embed/Nwg2JhP_rYc" width="640">
<!-- (embbed you arse) - another bulls'that causes blogger to hang F! . . . //-->

"WYSIWYG" . . . apx. -- the schematic

 PLOT

 TIMED to apx. match the video

B4 proceeding the 3-rd stage must assembled - each instance must be parametrized for continuity of discreet signal flow - if such is continuous and we get some oscillator running then it's enough to give it a GO - t.m. - the PCB must designed , made , perhaps some sh¡t more - then we run the visualization test - and the resource becomes a spare parts again - t.m. - design a PCB so the components are least affected - really annoying stuff that can be done if you have nothing else to do or need to test some new feature ...
[EOF]