Simplified versus "Real" Model -- osc. test
Update!: revised the RRIO-model though there's no any indication yet that it's to a better direction -- the fig. below , left
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amazingly or not amazingly -- the datasheet's 7404 inverter schematic does not enable to re-produce the I/O sink/source currents (and voltage levels) -- (1-st) the input sink of ~5.2µA from positive OUTP requires an additional diode shunted with over 1MΩ resistor but then the V.th drops 700 to 800 mV below the actual 1.62V (from what we can conclude the input transistor or it's E junction being something very different from conventional NPN) so what i utilized in my New CLM (component level model) was using a darlington for the input NPN of the "video amplifier"
that set the V.th and input source to OUTP low near correct - not minding about excessive input sink from OUTP high -- ignore (do not use) the schematic coz it is obviously not "the thing" . . . as in fact it does not have to be the thing -- what is required is something that in oscillators and crystal drivers would simulate near to real . . . i doubt any of the above 4 does good enough for X-tal osc. simulations . . .
Since there's no schematic/spec. avail for inner T-trigger -- the crap can't be fully validated -- "What's it worth ..." . . .
Cascading . . .
[Eop]
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