A Shifted Clock PWM test on 555 timers

the circuit ::

basically we have something here that resembles to a PWM but the circuit has several shortcomings

1. a bad selection of control voltage ranges that won't allow us to get intended PWM/delay control
2. while the clock generator is about independent of the supply voltage then other timers are not
3. the operation relies on successful fast cascaded triggering of the timers -- this might set a speed limits or other wise complicate the circuit

otherwise this DEMO is likely sufficient to give the reader a clue about what was intended -- AND-ing the shifted clocks at low duty versus OR-ing the clocks at high duty ---

--- the 0 to 100 % PWM is achievable either by designing the delay-/shift- timer to enable very narrow delays or pre-scaling it's start by it's time minimum constant -- adds complexity and degrades the accuracy and/or reliability

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A different approach -- using a simplified setup -- and more complex special situation handling ::

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[Eop]