Cap.-meter core by target type

"ceramic"

"polar"

both types need possible additional timing or/and displaying(+conversion4) circuitry -- that is not at the scope of this post - - - - we only examine the possible to achieve precision here

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Confirming the web cap-meter principle

the thing is theoretically capable of more precise function that it's claimed but in practice . . . i don't think it can do even twice the claimed 4%

. . . there are 3 to 6 constants that have to be set correct at the 10-th of a % precision -- but they are valid at a specific device working temperature + don't with-count / cancel-out the variation of parasitic properties of different capacitors

experiment ::

the diodes have a logarithmic voltage --or-- apx. Δi.D ~ exp(U.D) ... also the ΔU.c ~ exp(t) ...
... thus Δi.D ~ exp(exp(t)) --or-- if the U.c rises the frequency (Δi.D) must rise exponentially to provide ?? more linear U.c scale → the meter should run at constant outp voltage and varing frequency (4 starting ...)

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Latest experiments ...

a low voltage DS(hcottky)TL test ::

in :: https://www.falstad.com/circuit/circuitjs.html

in :: https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html

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j-Fet test ::

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scs test (a variety modified from the 7-th ed. GE Transistor Manual 1964) ::

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about :: the following is carried out on intent to find out the low-power-edge function of the scs / pulse-driven logic - - coz there're a lot of old discretes lying around nothing to do with - - in most cases the DTL is out performing such in a sense of power efficiency (but there are few exceptions and some conditional exceptions . . . most yet to be defined . . .)

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(-a-) -- incomplete design of low power HOLD capable RAM/Counter . . .

(-b-) -- i guess the proper operational voltage levels' range selection allows the following to operate without pulse amp stages . . .

(-c-) -- ↓it↓ draws about 10mA per cascade/stage for about 400kHz CLK src. (& takes an additional circuitry to read the trigger OUTP levels . . . e.g. adding even more power use in real implementation . . . )

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BjT versus OpAmp Staircase Generator

src::GE Transistor Manual 7-th ed. 1964 p.345
about :: it takes higher energy pulses + a NEG supply to run , (it may be not so as i quite don't get yet the anatomy of the thing but) it seems to have a worse linearity than the OpAmp v. though it also seems to keep it's levels longer in place and have a smaller variation in step size near zero to near Vcc (to "Zero the drift" it takes somewhat unreal precision tuning of the bias resistors . . . )

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PS! -- The RESET circuitry is NOT implemented for neither one of the gen.-s -- coz it'd result in slower simulation times - and it should be relatively easy to set up one for your needs
. . . also the use of low power oscillator requires a buffer 1 to not be affected from the fast-/"a low resistance value" -biasing resistors' reaction/(?bwd coupling)

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src::http://zpostbox.ru/g4_e.htm (Fig.28)
about :: the OpAmp v. accepts a higher variety of pulse voltages and tank-/integrator capacitor values -- the linearity is likely better than for bjt v. also the integration range is bigger (due lesser possible pulse amplitude values and the possibility to drive OUTP (Vsc) more close to upper rail . . .)

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