Virtual eval. of some LoVo OpAmp.-s

 is what the title says :

Text as a text :

Pass TEST *TLV314 -- struggles near rails but passes (1.8÷5.5V)* TLV2371 -- inp max 2.58V *TLV9102 -- struggles near the low rail but passes (2.7÷16V)* TL3472 -- inp min max 1.0 to 3.4 V OPA2990 -- inp max 2.49V *OP284 struggles near rails but passes better the TLV314 (3÷36V)* !!! -- MC33071 -- is over idealized model -- !!! (no significant problems) LMV824 -- inp MAX ? 3.1 to 3.8 V (exact value indeterminable) *LM7321 -- struggles near the rails but passes smoother than OP284 (2.5÷32V)* *LM6142 -- same as LM7321 but faster (1.8÷24V)* LM358 -- min max 404 to 2097 mV !!! a MACRO MODEL   ( the transistor model requires a scaled input to prevent the spurious oscillation !!! ) *AD8628 -- struggles near rails but passes somewhat worse the rest R2R passers (2.7÷5V)*

note : if there will be no spurious oscillations configuring the LM358 , LM324 as the unity buffer shown at above fig. then the sentence "the transistor model requires a scaled input to prevent the spurious oscillation" has no meaning in real-life otherwise the recommended biasing scheme is as http://tinyurl.com/yyvgyz32

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CD4013 by state machine

 about

model

* CD4013S.cir * Q iQ CPE R D S Vss Vdd .subckt CD4013S 1 2 3 4 5 6 7 14 .param zVt = 2/(5**.5+3) .param zVtH = zVt/5 * OUTPUT 1Ohm R20 121 1 1 R21 122 2 1 S1 14 121 114 0 FMSW S2 121 7 114 0 FMiS S3 14 122 115 0 FMSW S4 122 7 115 0 FMiS * GENERAL B1 99 0 V=V(15,7)*2 R1 99 0 10k B2 98 0 V=zVt R2 98 0 10k R3 14 15 5E5 R4 15 7 5E5 C4 15 7 5E-13 * C 103 * R 104 * D 105 * S 106 B3 103 0 V=if(V(99)>2,V(3,7)/V(99),0) B4 104 0 V=if(V(99)>2,V(4,7)/V(99),0) B5 105 0 V=if(V(99)>2,V(5,7)/V(99),0) B6 106 0 V=if(V(99)>2,V(6,7)/V(99),0) * ED EL iD D Q iQ R10 110 0 1k R11 111 0 1k R12 112 0 1k R13 113 0 1k R14 114 0 1k R15 115 0 1k * ED - enable data Q0 110 .machine .state sa0 0 .state sa1 1 .rule sa1 sa0 (V(110)>V(98)) & (V(103)>V(98)) & (V(111)<V(98)) .rule sa0 sa1 (V(110)<V(98)) & (V(103)<V(98)) & (V(111)<V(98)) .output (110) state .endmachine * EL - enable latch Q1 111 .machine .state sb0 0 .state sb1 1 .rule sb1 sb0 (V(111)>V(98)) & (V(110)<V(98)) & (V(103)<V(98)) .rule sb0 sb1 (V(111)<V(98)) & (V(110)<V(98)) & (V(103)>V(98)) .output (111) state .endmachine * INP Buff iD _Q2 112 .machine .state sc0 0 .state sc1 1 .rule sc1 sc0 (V(112)>V(98)) & (V(104)<V(98)) & ( ( (V(110)>V(98)) & (V(105)>V(98)) ) | ( (V(110)<V(98)) & (V(113)>V(98)) ) ) .rule sc0 sc1 (V(112)<V(98)) & ( ( (V(110)>V(98)) & (V(105)<V(98)) ) | (V(104)>V(98)) ) .output (112) state .endmachine * INP Buff D Q2 113 .machine .state so0 0 .state so1 1 .rule so1 so0 (V(113)>V(98)) & (V(112)>V(98)) & (V(106)<V(98)) .rule so0 so1 (V(113)<V(98)) & ( (V(112)<V(98)) | (V(106)>V(98)) ) .output (113) state .endmachine * OUTP Buff Q Q3 114 .machine .state sd0 0 .state sd1 1 .rule sd1 sd0 (V(114)>V(98)) & (V(106)<V(98)) & ( ( (V(111)>V(98)) & (V(112)>V(98)) ) | ( (V(111)<V(98)) & (V(115)>V(98)) ) ) .rule sd0 sd1 (V(114)<V(98)) & ( ( (V(111)>V(98)) & (V(112)<V(98)) ) | (V(106)>V(98)) ) .output (114) state .endmachine * OUTP Buff iQ _Q3 115 .machine .state sx0 0 .state sx1 1 .rule sx1 sx0 (V(115)>V(98)) & (V(114)>V(98)) & (V(104)<V(98)) .rule sx0 sx1 (V(115)<V(98)) & ( (V(114)<V(98)) | (V(104)>V(98)) ) .output (115) state .endmachine .model FMSW SW(Ron=1 Roff=.1G Vt={zVt} Vh={-zVtH} Ilimit=.1) .model FMiS SW(Ron=.1G Roff=1 Vt={zVt} Vh={-zVtH} Ilimit=.1) .ends

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LM311 & LM393 common mode sensitivity test

LM311 auto-biasing test

LM311 optimal (most sensitive) input voltage offset TEST

LM393 optimal (most sensitive) input voltage offset TEST

LM393 oscillator forcing the input to it's optimal common input voltage offset ... Vee/Vss/-Vs

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More experimental spice models

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Digital (SN7400 , SN7404 , SN7414 , SN7474 , SN7486 , SN74112)

how and when i use ↑these↑ :: is to determine the apx. dynamic power draw , relative I/O states , etc.

it is not advised to use these in complex digital simulations coz such takes excessive time ... and serves no conceptual purpose

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TLC555 (Ti's P-Spice , + a Less simplified , + a More simplified)

since my first Ti's TLC variant model conversion for the LTSpice got destroyed  in OS reinstall - i haven't had time to recreate it . . . so -- the simplified /!\ ideal /!\ models are "close enough" to run a principial simulations -- one must address the shortcomings of such . . . + moreover the ideal models lack some required damping and referencing internal components ← means: the simulation may hang due the shortcomings from such = all pins must be connected or referenced through R or R C networks ← the values of which may be crucial to simulation "stability" (not to hang , etc. ...)

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"DIGITAL" PASS GATE (not fully verified but so far a will do v. -- with 2 simulation examples)
(related post : Comparing TTL JK Triggers' Logic Designs)

example use

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Some experimental (mostly CLM) models

► Analog ◄ about ::

the models are (behave) sometimes (at some circuits) better than the manufacturer provided ones . . . anyway they are the way slower -- so , using the multiples of them dramatically slows down the simulation . . . /!\  since the op amps basically act all the same  /!\ it is advised to use similar Is , Vs , GBW , SR or better LTSpice's "built in" substitutes in case the simulation speed matters

________________________________________________________________ misc. files _remove_temporary_files.bat Deletes unused simulation data files ~about_these_files.txt ↑← This File →↓ ________________________________________________________________ .cir models AD633.asy ad633.cir Analog AD633 P-Spice Model of the analog 4-quadrant multiplier AD633AN.asy AD633AN.cir Simplified AD633 macro model AZ431.asy AZ431.cir TL431 functional analog of the Programmable Shunting Voltage Reference/-Regulator LM311.asy LM311.cir Voltage Comparator LM324.asy LM324.cir Op-Amp LM393.asy LM393.cir Voltage Comparator LT1011.asy ! built-in LTSpice built in model (at the default Path) of the Voltage Comparator (LM311) NE555.asy ! built-in LTSpice built in model (at the default Path) of the NE555 ________________________________________________________________ .asc subcircuit models AN6914.asc AN6914.asy LM393 component level functional anaolog of the OC OUTP voltage comparator K554CA3-A.asc K554CA3-A.asy LM311 component level functional anaolog of the OC-/OE OUTP voltage comparator KA7805.asc KA7805.asy CLM (component level "model" / functional anaolog) of the 3-terminal linear voltage regulator LM2903.asc LM2903.asy LM393 component level EXPERIMENTAL anaolog of the OC OUTP voltage comparator LM317T.asc LM317T.asy CLM of the 3-terminal linear voltage regulator LM324XI.asc LM324XI.asy CLM of the Op-Amp NE555ic.asc NE555ic.asy CLM KP1006BU1.asc KP1006BU1.asy CLM of the NE555 Kp140yg1208cx.asc Kp140yg1208cx.asy µA776 CLM Op-Amp (recommended at 15µA control current) KP140yg1408vA.asc KP140yg1408vA.asy LM308 CLM Op-Amp ________________________________________________________________ .asc circuit DEMO simulations NE555-TEST-Es1117-Plus.asc NE555-TEST-Es1117-Plus.plt NE555 - parameters TEST NE555-TEST-Es1117-Plus-A.asc NE555-TEST-Es1117-Plus-A.plt NE555 - parameters TEST 2 NE555-TEST-Es1117-Plus-B.asc NE555-TEST-Es1117-Plus-B.plt NE555 - parameters TEST 3 GCx93 - CLM - Test - Q104-mp.asc GCx93 - CLM - Test - Q104-mp.plt LM393 - test K554CA3 - CLM - Test - Q110-mp.asc K554CA3 - CLM - Test - Q110-mp.plt LM311 - OE test K554CA3 - CLM - Test - Q112-mp.asc K554CA3 - CLM - Test - Q112-mp.plt LM311 - OC test Random - Op-Amp - TEST - iZ-8aF-xF.asc Random - Op-Amp - TEST - iZ-8aF-xF.plt LM324(XI) CLM test ________________ ** [EOF]

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