some BJT dependencies -- the simualation vs. the d/s

the ß by Ic (has a very poor matching)

the saturation region of the collector (has a better matching)

junction capacitance (a realistic matching)

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Op amp output stability

The component level versus the macro model ::

 

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Op Amp dif. CM inp. imp.

 The differential and common mode input impedance of the op amp transistor models ...

 

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The circuits for determining the AvOL (open loop gain) of the op amp

´ 741 ::

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LM324 equivalent transistor model ::

Av ≈ 1.42·10⁶

Av ≈ 1.43·10⁶

Av ≈ 1.48·10⁶

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Univeral Op Amp for probing the CM input range

(in pictures)

A universal ("enough") Op Amp

Old CM Inp-rg. test

New CM Inp-rg. test

 

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Pos. fbk. Op. Amp. - (spice) noise

see also : Dif. Pos.-fbk. op.-Amp.

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about LM324 , uA741 , TL071 , LM308 :

  compared to conventional biasing schemes : 

the pos.-fbk scheme has more poor noise and frequency characteristics but it enables to use the feedback shoulder to excite a crystal or reduce the input current . . .

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another inductance meter concept

a dummy sine generator :

Op Amp version :

the x = Δf( L( f ) ) = – 2 · Δf / ( (2π) ²­ · C · f ³ )

where Δf = f(40uH) - f(42uH)

the  y = ΔL( f ) = L(42µH) – L(40µH)

and the best match for the ΔL is a non-std. average E( x , y ) = 2 · x · y / ( x + y )

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How tomeasure the inductance with a resistor , a coil and a square wave source

about
PS! note : the V_LMAX and the I_A are the max. V and I peak-values developing in the circuit at the run time
+ in the above simulation the formula does NOT account the internal resistance of the voltage source (which it should !!! (for the more accurate result))

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L - meter

src :: Cheap and easy inductance tester uses few components - EDN

test ::

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LTspice C-/V - sources terminals' polarity

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CMOS Op Amp - simplified models

 arctan()/(π/2) versus tanh() ::

PS! :: this model was created for the fast retrieving of the effect and the response of the particular P-MOS input stage ... the output starts behaving weird near the rails !!!

which means the model cannot be used for conventional simulation purposes !!!

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! Update ::

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 the (simplified-inexact MCP601) model for conventional use (compared against the Ti-s LMV831) ::

? interestingly the Ti's model has a suspicious behaviour on the input exceeding the supply rails ???

? the P-Spice model of the LMV831 accounts the common mode range ending some 1V below the upper rail so it likely suits better the simulation that needs to take into account that limitation . . . my simplified MCP601 model is brought below ::

Listing of the : MCP601SM.cir ::

* Universal Op Amp * IN NI OUT Vss Vdd .SUBCKT MCP601SM 1 2 3 4 5 PARAMS: Rt=18 gms=1 nms=1 pms=.5 * USE C=30 PF IN MAIN CIRCUIT (CA TO CB). * INPUT R1 5 51 R=Rd R2 5 52 R=Rd M1 55 55 51 51 PcMfT m=pm M2 50 55 52 52 PcMfT m=pm C1 50 55 .2p M3 43 1 50 50 PcMfT m=pm M4 44 2 50 50 PcMfT m=pm M5 43 44 41 41 NcMfT m=nm M6 44 44 42 42 NcMfT m=nm R3 41 4 R=Rs R4 42 4 R=Rs I1 55 4 35u load * DIFFERENTIAL R6 8 17 100k B1 7 17 V=V(43,44) R7 7 17 10k C2 7 17 {srf} * MEDIAN / CLIPPER / Vcp B5 10 0 V=V(5,4)/2-vfz R5 10 0 10k * CP B3 8 0 V=(V(4)+V(5))/2 R8 8 0 10k * MED B11 8 13 V=V(10) B12 12 8 V=V(10) D1 6 12 SjD D2 13 6 SjD R11 11 6 1 * GAIN / SLEW L1 10 8 300n * V.med modified ! B4 10 11 I=(V(5,4)/2+vfz)*tanh(2**bm*V(7,17))/10k R10 11 8 10k C3 11 8 {srf} * OUTP B2 9 8 V=V(11,8) R9 9 8 R=10k C4 9 8 {srf} R12 9 3 R=30 .param gm={gms} .param nm={nms*gm} .param pm={pms*gm} .param Rd={Rt*2/6} .param Rs={Rt-Rd} * .param bm=13.25 .param bm=6.223 .param vfz=0.45 .param srf={0.23n/2} .MODEL NcMfT NMOS(L=2u W=42u KP=35u LEVEL=1) .MODEL PcMfT PMOS(L=2u W=84u KP=7u LEVEL=1) .MODEL SjD D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon) .ENDS

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