Progressive current limiting

Figures ::

Legend :: opamp.Q1 mirrors the current at R5 , opamp.Q2 limits the current progressively ... and incase of the SC it cuts the output the more off the lower is the output voltage -- so there's double level progressive limiting (the fig.2 shows the 1-st and the fig.-s 3 to 5 show the 2-nd - a short circuit - limiting levels) . . . the resistor values for R24 to R26 and R21 , R22 , also for the R14 may need to be adjusted to get the real build of the circuit stable (maybe it takes more adjustments -- but these are known to be more likely critical at this stage of dev.)

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[Eop]

5V regulator variants for 6F22

LDO utilizing a low R.DS of a MOSFET

a switchng variant of the prev. LDO !! no current limiting nor other specific situation handling !!

( !note : of course the OUTP loading is inverse proportional to R.int.BATT )
Component count optimized v. of EF regulator

Max. precision v. of prev.

-- the fold-back v.

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[Eop]

testing textbook voltage regulators

the src. A (fig. ⓐ) - won't start up with higher ß , silica "western" transistors

if we add a "startup**" it won't be overload proof -- it is possible to set there a time constant based startup "boost" that charges the output capacitor to near nominal output at no or moderate load connected . . . why all this fuzz - i just studied the circuit for it's simplicity . . .
. . . the next is what i came out as a near reasonable practical solution for the type of regulator (or what's left of that type)

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update: an alternate "startup**" v. that is still overload proof only it requires extra "Discharge" button to get off the "output disabled mode" -- to make it also "user proof" requires a special discharge or power button so that the discharge engages only when external supply can't charge the caps. -- all cool the simlpe things are not simple . . .

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the src. B (the leftmost fig.) -- works good as shown as long the input voltage is higher the output plus NPN-s BE vtg. drop + Op Amp-s incapability to reach positive rail some 1 to 2 V

if we power the regulator control circuitry from separate supplies - we get the foldback v. of the above src.

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[Eop]

How to kill your LDO

extends http://chpsndtch.blogspot.com.ee/2015/05/two-random-voltage-regulators-practical.html , http://chpsndtch.blogspot.com.ee/2015/04/regulator-redesign-lab-as-always.html

Getting some numbers . . .

a quick fix + improved zener
(*update :: i used in practice a darlington - not the super ß - "power switch" - this cfg. seems to have a better supply-/load rejection than below ↓↓)

insane . . . improving Vs rejection + "digital" current limit

"back to analog" -- adding batteries . . .
 (*update :: see above ↑↑)

(hope idon't uploadthis2wce) -- a fold-back sc current Lim.

[EoP]

Regulator Redesign (/Lab -- as always . . .)

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2015-04-15 ::
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 . . . trying to "de(/un)-bug" the last design from prev. post -- normalize power range , minimize the error . . .

+ a modified v.'s foldback diagram

Customizing/"improving" the 78Lxx for 1.2V

i only guess it's 3.0V
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2015-04-16 ::
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"Minimizing Compile" , exploring the switcher mode v. , experimenting with foldback . . .

thought to use the LT's µ-P 2.5V LDO -- but the 3uA is likely causing it's instability in high loads env.

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2015-04-17 ::
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Optimizing "Design"

Update! :: the foldback re-visited . . .

Update+ :: ±10µV version ::

Update+ :: ±12µV version with foldback updated to support high load capacities (no frequency test - what so ever- carried out + i donno how to thermal compensate - /!\ so i never do /!\) e.g. you have to recalculate the design before any attempt to assemble it

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