src :: http://www.brown.edu/Departments/Engineering/Courses/En123/Lectures/DAconv.htm
modified
??  sounds "fun"
best guess :: The Pipelined ADCs
src::not found at web
apx. guess of the ADC circuit layout and biasing resistors
related ::http://chpsndtch.blogspot.com.ee/2017/08/4bitadcimprovement.html
base/radix 3 ver. :: uses the same amount of ics per cascade  but has "exponentially" higher resolution
↑ the radix 3 output can be converted to binary by summers  for example ↑
something similar found at www :: https://www.researchgate.net/publication/220365717_A_LowPower_Capacitive_Charge_Pump_Based_Pipelined_ADC
at the sown ADCs when switched to 5V single supply and the CMOS comparators and op amps  the least can be extended with 74HC125 or ↓ 74HC126 ↓ (to gain the OC OE functionality of LM311) . . . in other words by these changes the circuit can be made faster

↑ there's some optimistic 2.5µs read window ↑ to stay at the precision of the shown 0 to 26 e.g. 27 level of quantization . . .
As a target of these tests  i attempted to find suitable ADC  DAC combination to set up a successive approximation ADC
modified
??  sounds "fun"
best guess :: The Pipelined ADCs
src::not found at web
apx. guess of the ADC circuit layout and biasing resistors
related ::http://chpsndtch.blogspot.com.ee/2017/08/4bitadcimprovement.html
base/radix 3 ver. :: uses the same amount of ics per cascade  but has "exponentially" higher resolution
↑ the radix 3 output can be converted to binary by summers  for example ↑
something similar found at www :: https://www.researchgate.net/publication/220365717_A_LowPower_Capacitive_Charge_Pump_Based_Pipelined_ADC
at the sown ADCs when switched to 5V single supply and the CMOS comparators and op amps  the least can be extended with 74HC125 or ↓ 74HC126 ↓ (to gain the OC OE functionality of LM311) . . . in other words by these changes the circuit can be made faster



CMOS Radix3 :: 2.5x faster than a "slow" LM324↑ there's some optimistic 2.5µs read window ↑ to stay at the precision of the shown 0 to 26 e.g. 27 level of quantization . . .
As a target of these tests  i attempted to find suitable ADC  DAC combination to set up a successive approximation ADC
 as by adding cascades to shown cascaded(/pipelined) ADCs  the transition delay to LSBs increases  they don't much improve the final conversion speed
 basically the cascaded converters are a "Static SAR DAC" variants  the SA delay still remains
 i must rethink the concept here
  either should use a parallel converter
 or try to incorporate/integrate a differential approach
[Eop]