4-bit DAC and ADC test

src :: http://www.brown.edu/Departments/Engineering/Courses/En123/Lectures/DAconv.htm

modified

?? -- sounds "fun"

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best guess :: The Pipelined ADC-s

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src::not found at web

apx. guess of the ADC circuit layout and biasing resistors

related ::http://chpsndtch.blogspot.com.ee/2017/08/4-bit-adc-improvement.html

base/radix 3 ver. :: uses the same amount of ic-s per cascade -- but has "exponentially" higher resolution

↑ the radix 3 output can be converted to binary by summers -- for example ↑
something similar found at www :: https://www.researchgate.net/publication/220365717_A_Low-Power_Capacitive_Charge_Pump_Based_Pipelined_ADC

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at the sown  ADC-s when switched to 5V single supply and the CMOS comparators and op amp-s -- the least can be extended with 74HC125 or ↓ 74HC126 ↓ (to gain the OC OE functionality of LM311) . . . in other words by these changes the circuit can be made faster

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CMOS Radix-3 :: 2.5x faster than a "slow" LM324

↑ there's some optimistic 2.5µs read window ↑ to stay at the precision of the shown 0 to 26 e.g. 27 level of quantization . . .

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As a target of these tests -- i attempted to find suitable ADC - DAC combination to set up a successive approximation ADC

• as by adding cascades to shown cascaded(/pipelined) ADC-s -- the transition delay to LSB-s increases -- they don't much improve the final conversion speed
• basically the cascaded converters are a "Static SAR DAC" variants -- the SA delay still remains
• i must rethink the concept here
  
  • -- either should use a parallel converter
  • or try to incorporate/integrate a differential approach

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[Eop]

Virtually Testing the Speed Limits of the Common Opto-Coupler

in experiments ::

a weak-/narrow- pulse drive ::

a balanced-NRG input drive ::

((( Näed , -- see ahv pani ↑nad↑ isegi õiges järjekorras . . . seekord !? )))

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[EoF]

A Shifted Clock PWM test on 555 timers

the circuit ::

basically we have something here that resembles to a PWM but the circuit has several shortcomings

1. a bad selection of control voltage ranges that won't allow us to get intended PWM/delay control
2. while the clock generator is about independent of the supply voltage then other timers are not
3. the operation relies on successful fast cascaded triggering of the timers -- this might set a speed limits or other wise complicate the circuit

otherwise this DEMO is likely sufficient to give the reader a clue about what was intended -- AND-ing the shifted clocks at low duty versus OR-ing the clocks at high duty ---

--- the 0 to 100 % PWM is achievable either by designing the delay-/shift- timer to enable very narrow delays or pre-scaling it's start by it's time minimum constant -- adds complexity and degrades the accuracy and/or reliability

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A different approach -- using a simplified setup -- and more complex special situation handling ::

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[Eop]

Testing couple of rectifier circuits from datasheets

The following schematics are from LT1122 and LTC1047 d/s-s
while the first performs more than good -- then on a contrary i had to modify the 2-nd

↓Src::LT1122 datasheet -- not tested at various frequencies nor input amplitudes/wave-forms
 

↓Src::LTC1047 datasheet -- the 10kHz seems to be the limit for the outp integrity here

//// recently i noticed something while using a variant of the ideal diode circuit as shown in the "Low Voltage Op-Amps -- in-simulation TEST" -- so i am about to test through all "Absolute circuits" for their particular peculiarities . . .

↓Src::NE5535 datasheet

↓Src::http://nptel.ac.in/courses/117107094/17

↓Src::https://www.planetanalog.com/author.asp?section_id=3065&doc_id=562650 -- the circuit can do just at about 200kHz !? //// note :: i forgot to change the counter-weight 1N4148-s to 1N34-s below (their effect is not studied here , purpose = pending -- what seems obvious is not always that -- it must be verified whether there should be counter-balance for rectifying diodes or not . . .)

↓Src::https://forum.allaboutcircuits.com/threads/a-full-wave-precision-rectifier-query.9821/ --

↓Src::http://sound.whsites.net/appnotes/an001.htm -- it can go up to the limits defined by the frequency & slew of the Op Amp in use ((!? amazing circuit ?!))

↓Src::http://www.learningelectronics.net/worksheets/opamp8.html --the ® had a "bug" so i made random guesses . . . came out as good as previous ((at least what it seems so far ?)) /// edit : the R9 should be Rcp (although there seems no significant current to/from GND from/to U2.non-inverting_input) /// the input signal amplitude range is ±1.8V @ ±5V supply and ±10V @ ±15V supply -- simplified to a line equation y = ax + b where a = 1.219512195 , b = 2.804878049 , y = VsupTOT/2 , x= abs(±VmaxINP) referenced to the GND ( = Vsup "median" )

updates 'll follow ...

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[Eop]