about the Rightmost CC-(?source)-sink from http://chpsndtch.blogspot.com/2014/07/re-non-real-world-constant-current.html - the CZ("title") used there - teh variations 1-st -
- the ® it starts to generate(oscillate) @ 130Hz (there might be problems using such in US 60Hz(120Hz full-wave rectified) grid) - PS! i mostly do fast designs for "feature (exists/works)" chk.-s - i don't fully test nor analyze 'em - unless i intend to build smth. in real
- this is actually the last modification (my v. numbering is not continuous - i leave gaps to dev the prev to that point 1) . . . so, it may be thought such improves the Zener plot curve - as in fact in such a low Vtg. it much does not . . . . . . it had some adv.-ge to ® whitch i don't already remember . . .
- the pre-last v. that turned out to be most successful in extending the "in-range" ??? range ^_,^ - so as it /!\ promises can be used up to 16kHz if it stays in specified range (gets shrinked @ higher fq.-s) PS! my attempts to avoid re-generating is based on error trial + heuristic prediction - i don't do wave theory too well - t.m - i can't tell if it applies to real world or is it a numerical integer sync./de-sync. from simulator engine's simplifications - should be verified with the scope ((for a real build) which i don't have)
- the next to the ® v. (e.g. the 2-nd v.) - a final of 1-st modification series - here everything to right from , including the , - ( R5 , R2 ) is a constant current sink defining an opening point for PNP on R1 . . .
. . . i guess this phenomena is worth some further look . . .
. . . trading off the startup/NRG to range and Fq. . . . don't ask me how - i just work here XD
:: it seems the TL's error tracking feature is adaptable to different supply schemes . . .
. . . re- :: hi-ko ??? -- :: it seems the TL's error tracking feature is adaptable to different supply schemes ::
[EoF]
Showing posts with label blogger's malfunction/peculiarity. Show all posts
Showing posts with label blogger's malfunction/peculiarity. Show all posts
Wednesday, July 9, 2014
Tuesday, July 8, 2014
TL431 lab 2
extends the http://chpsndtch.blogspot.com/2014/03/tl431-test.html
. . . made a bit mdf.-s to . .
PS! it's nothing final - just a temporal stop of the exploration of it's behavior . . . the resistance-step response's quite not what we want to see
An experimental design to feed low voltage opAmp or comparator . . .
+ the bullshit - i can't design the switching regulators too well (if at all) ::
. . . but i needed to test my experimental comparator - which i also can't design ^_^ but it seems to do smth.
the funny thing about it is that i tried to use as few components as possible - ↑ here we go ↑ - the least number of components for BJT-only low-sup.-vtg. comparator (i didn't especially sweat on ot's output stages design . . . ) . . . -- . . . the summary here is that a FET.v would be more capable (this is the 1 used in prev. figure/ /!\ /!\ /!\simulation /!\ /!\ /!\ however)
:: the TL'-s error tracking feature looks like to be exportable
[EoF]
. . . made a bit mdf.-s to . .
PS! it's nothing final - just a temporal stop of the exploration of it's behavior . . . the resistance-step response's quite not what we want to see
An experimental design to feed low voltage opAmp or comparator . . .
+ the bullshit - i can't design the switching regulators too well (if at all) ::
. . . but i needed to test my experimental comparator - which i also can't design ^_^ but it seems to do smth.
the funny thing about it is that i tried to use as few components as possible - ↑ here we go ↑ - the least number of components for BJT-only low-sup.-vtg. comparator (i didn't especially sweat on ot's output stages design . . . ) . . . -- . . . the summary here is that a FET.v would be more capable (this is the 1 used in prev. figure/ /!\ /!\ /!\simulation /!\ /!\ /!\ however)
:: the TL'-s error tracking feature looks like to be exportable
[EoF]












