Friday, July 17, 2015

Design Concept for 9►5V "PWM"

Quick tests :: both are using random interpreted 1.2V oscillators that may not perform so good in practise at that voltage -- the 5V adjusting network is poor , minimal - i primarily needed the P.OUT capability . . .

A) ?? 230kHz

B) -- designed 1-st re-adjusted later 40kHz


Wednesday, July 15, 2015

Basic Logic Test

(how to verify a custom logic)
an aspect (´-ry) to notice on plot - what it seems -
is that the V.X0 would reach the OUTP.LO not after the VX2
(the 2-rys are rise and fall slope , the V.X5 shape)
  • a minimal* sufficient requirement for OUTPUT is that it can drive at least the 5 inputs (a 4-stage* counter/-decoder) -- to be sure of that here the 6 inputs are driven
  • also the signal paths should be terminated with (a loaded +/by a floating = 2x) inverting buffers
    (it'd be better to terminate the floating one (last) to signal threshold with resistors -- but such not practical here coz it'd take to constantly keep a track on the 3shold of the changing design)

another pointless post about custom 1.2V logic

X-perimental Schmitt Trigger

the higher power v. of ?the lower power v.

The TEST ::
 the Schmitt can go about 3.6MHz . . . the logic follows below 1MHz
(should revisit one or the other)

The uncompacted sub-circuits ::
teh XC-trigger almost but not exactly the JK-trigger
The 3ger ::
confirming hysteresis