Wednesday, July 15, 2015

Basic Logic Test

(how to verify a custom logic)
an aspect (´-ry) to notice on plot - what it seems -
is that the V.X0 would reach the OUTP.LO not after the VX2
(the 2-rys are rise and fall slope , the V.X5 shape)
  • a minimal* sufficient requirement for OUTPUT is that it can drive at least the 5 inputs (a 4-stage* counter/-decoder) -- to be sure of that here the 6 inputs are driven
  • also the signal paths should be terminated with (a loaded +/by a floating = 2x) inverting buffers
    (it'd be better to terminate the floating one (last) to signal threshold with resistors -- but such not practical here coz it'd take to constantly keep a track on the 3shold of the changing design)

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