Thursday, December 28, 2017

www voltage multiplier test

src ::
(i donno why they have to post circuits in the web that add up to the climate warming ...)

mod/fix ::
(the circuit'd do better with true complement wave drive -- e.g. -- a RS digital flop driving two powerful buffers -- in our case -- 555-s)


Tuesday, December 26, 2017

the Actual/Built LED verifier

as i was not about to build a PCB for this the sot-jFets were not used . . .

Spice design ::

Real build ::


Friday, December 22, 2017

Comparing Constant Current Circuits (to sort/verify the LED-s with)

▼Fast/Simple/Robust/Trivial Op-Amp + BJT Setup▼
→ apx. 16mA ±30µA(0.2%)
▼Complex/Trivial Op-Amp + BJT Setup▼
 → apx. 18mA ±24µA(0.1%)
▼Simple/Experimental BJT Setup ( !? the Best ?! )▼
→ apx. 18mA ±60nA(0.0003%) 
▼Full/Trivial BJT + N-jFet Setup ( also better than any op-amp variant ??? )▼
→ apx. 18mA ±300nA(0.002%) 
▼Complex/Experimental Op-Amp + MOS-Fet Setup▼
(likely worse than it's BJT alternate -- the 2-nd ↑↑ fig. )
→ apx. 18mA ±120µA(0.7%) 
▼Trying to get it right here▼
-- it seems that the op-amps should be fed from the separate supplies or otherwise the PSRR won't recover the precision reached at reference voltages
→ apx. 18mA ±48µA(0.3%) 

((the work is in progress ...))

If you are stupid then knowing the right Op-Amp-s could save your day
(the node "SE" had the greatest error although the node "a0" has the least ??? -- about LT1012A)
→ apx. 18mA ±10µA(0.06%)

-------- Update 2017.12.24 ::

▼a conditional opposite to "If you are stupid then knowing the right Op-Amp-s could save your day"▼

→ apx. 18mA ±7µA(0.04%)
a "Russian LM308" **
** it's nearest LT's substitute (so far)


Wednesday, December 20, 2017

Saturday, December 16, 2017

Random Op-Amp TEST - 2

Heuristic Test /// note that no matter these results may seem poor , they are poor in conjunction to the (perhaps a poor) test setup and relative to each other - - - i never test poor amplifiers (e.g. something that i know will fail my application) or do not test such without especially denoting it . . . as in fact the TLV314 was the best performer of a previous tests of it's kind (Low-power , Low-Voltage CMOS Op Amps) - - - here we have a high slew rate and/or high slew rate to bandwidth ratio Op Amps tested (where the TLV314 is just for comparison)

Fuzzily about how it works


Monday, December 11, 2017

Random Op-Amp Test

it fails the internal ground test ← which is somewhat expected for the "Smart" OP-Amp

Test #2 , as it turned out with erroneous formula guess
+ i must read the specs again about common . . . differential mode range

(the next "Error" will reject it as not LTSpice compatible . . .)

Test #2 again , this time with correct formula but with a different OpAmp to compare to

Test #3 -- about the biasing specifics

Comparative Test #4

PS! the integrity of this test setup has not yet been fully verified !!!

[in progress]


Saturday, December 9, 2017

500kHz DAC

the 2.5V ref. is provided for possible more exact v. of this -- for example -- forward normalizing the output as Uout=Uin*Vref/(Vsup/2)

Comparative ref. test

Experimental /// Alternative (the best) /// Datasheet (the 2-nd best)

it seems that the inverter/comparator type ADC ↓↓ is the fastest here
now with CMOS-Comparators ((i tiled it up intuitively -- a top-down design -- surprisingly or not it came out the same as at the linked one ↑above↑))

(the chosen resistor values may be not the optimal or not the realistic 1-s)


Monday, December 4, 2017

yet another DAC

it seems the Spice Models do "Count" -- although this may seem a far shot -- then there is actually a real life analogy or at least a strong potential -- that the certain components or a combination of produces far better results than some others !!

perhaps continued ...

optimistic with "continuous"/slow slope signal


Thursday, November 30, 2017

4-bit DAC and ADC test

src ::


?? -- sounds "fun"

best guess :: The Pipelined ADC-s

src::not found at web

apx. guess of the ADC circuit layout and biasing resistors

related ::

base/radix 3 ver. :: uses the same amount of ic-s per cascade -- but has "exponentially" higher resolution

↑ the radix 3 output can be converted to binary by summers -- for example ↑
something similar found at www ::

at the sown  ADC-s when switched to 5V single supply and the CMOS comparators and op amp-s -- the least can be extended with 74HC125 or ↓ 74HC126 ↓ (to gain the OC OE functionality of LM311) . . . in other words by these changes the circuit can be made faster

CMOS Radix-3 :: 2.5x faster than a "slow" LM324

↑ there's some optimistic 2.5µs read window ↑ to stay at the precision of the shown 0 to 26 e.g. 27 level of quantization . . .

As a target of these tests -- i attempted to find suitable ADC - DAC combination to set up a successive approximation ADC
  • as by adding cascades to shown cascaded(/pipelined) ADC-s -- the transition delay to LSB-s increases -- they don't much improve the final conversion speed
  • basically the cascaded converters are a "Static SAR DAC" variants -- the SA delay still remains
  • i must rethink the concept here
    • -- either should use a parallel converter
    • or try to incorporate/integrate a differential approach


Saturday, November 25, 2017

Virtually Testing the Speed Limits of the Common Opto-Coupler

in experiments ::

a weak-/narrow- pulse drive ::

a balanced-NRG input drive ::

((( Näed , -- see ahv pani ↑nad↑ isegi õiges järjekorras . . . seekord !? )))


Saturday, November 18, 2017

A Shifted Clock PWM test on 555 timers

the circuit ::

basically we have something here that resembles to a PWM but the circuit has several shortcomings
  1. a bad selection of control voltage ranges that won't allow us to get intended PWM/delay control
  2. while the clock generator is about independent of the supply voltage then other timers are not
  3. the operation relies on successful fast cascaded triggering of the timers -- this might set a speed limits or other wise complicate the circuit
otherwise this DEMO is likely sufficient to give the reader a clue about what was intended -- AND-ing the shifted clocks at low duty versus OR-ing the clocks at high duty ---

--- the 0 to 100 % PWM is achievable either by designing the delay-/shift- timer to enable very narrow delays or pre-scaling it's start by it's time minimum constant -- adds complexity and degrades the accuracy and/or reliability

A different approach -- using a simplified setup -- and more complex special situation handling ::


Thursday, November 16, 2017

Testing couple of rectifier circuits from datasheets

The following schematics are from LT1122 and LTC1047 d/s-s
while the first performs more than good -- then on a contrary i had to modify the 2-nd

↓Src::LT1122 datasheet -- not tested at various frequencies nor input amplitudes/wave-forms

↓Src::LTC1047 datasheet -- the 10kHz seems to be the limit for the outp integrity here

//// recently i noticed something while using a variant of the ideal diode circuit as shown in the "Low Voltage Op-Amps -- in-simulation TEST" -- so i am about to test through all "Absolute circuits" for their particular peculiarities . . .

↓Src::NE5535 datasheet


↓Src:: -- the circuit can do just at about 200kHz !? //// note :: i forgot to change the counter-weight 1N4148-s to 1N34-s below (their effect is not studied here , purpose = pending -- what seems obvious is not always that -- it must be verified whether there should be counter-balance for rectifying diodes or not . . .)

↓Src:: --

↓Src:: -- it can go up to the limits defined by the frequency & slew of the Op Amp in use ((!? amazing circuit ?!))

↓Src:: --the ® had a "bug" so i made random guesses . . . came out as good as previous ((at least what it seems so far ?)) /// edit : the R9 should be Rcp (although there seems no significant current to/from GND from/to U2.non-inverting_input) /// the input signal amplitude range is ±1.8V @ ±5V supply and ±10V @ ±15V supply -- simplified to a line equation y = ax + b where a = 1.219512195 , b = 2.804878049 , y = VsupTOT/2 , x= abs(±VmaxINP) referenced to the GND ( = Vsup "median" )

updates 'll follow ...


Tuesday, October 17, 2017

LM317 component level versus LT317 macro model

about the real things LM317x LT317x

simulation models (Custom against Linear)

a curious thing ↑here↑ is that the CLM(component level model) seems to be more stable than the ↓next↓ macro (more simplified) model

Models about ::