CMOS osc.-s TEST

! notice the word "test" above !!!

in images

originally with j-FET (← to cancel out BJT feedback to quartz) and BJT (← the low power side) while i realized the j-FET can pretty much do the thing on it's own . . .

the copy paste from NXP-s datasheet (the R3 + diodes added as a speculative ¹ startup booster / ² frequency booster / ³ exponential atenuator)

"alternate compile" of the above prev. (not thoroughly studied !!!)

what the NXP d/s does not tell you . . . about 32kHz quartz (the "C5" is the type of magic wand here)
...

trivia CD4060BC

• (Simulation speed) Fast model
• !!! Fixed to Spice Global GND
• integral for external Clk only !!!
• using Ti-s Data sheet acquired from Harris Semiconductor SCHS049C − Revised October 2003 v.

Test/Result uses 2x(CD4003/4013 to pad for missing outputs - inverting outputs not implemented but for φ̅₀̅)

Internals (barely noticeable on schematic -- the p9 & p10 use noninverting output buffers CD4060jf4V.asc -- not shown below)

---

[Eop]

DAC test

CD4069 outputs are referenced to supply median

checking if such produces a linear ramp . . .
all fun of resolving a simple 3 - supply voltage divider (finding the formula for U_X)

. . . checking if such produces a linear ramp in excel . . .
-- the value 1/2 used in LT Spice seems to be incorrect . . .

---

[Eop]

CD4003 (К176ТМ1)

e.g. what to do with old stuff ...

Simplified CMOS setup - to gain reasonable simulation speeds ...

one half of the chip (the 4011 and -69 have the same I/O/supply scheme) :

extendable counter setup :

[Eop]