ADC variant using the OC outp mod from the prev. post

lately , in conjunction with the other work , i noticed that the software ADC , i fast wrote for one of the experiments , actually can be implemented pretty much "as is" and on the real components ...

here's the ADC variant (the only problem will be to keep the voltages steady enough that the output would ... exist ! ...)

in above the voltages Vr0 to Vr3 (near) match the voltages Q1 to Q4 (the least being generated by the hw implementation of the ADC)

the fascinating thing is the relative simplicity of it (although the single chip DAC or µC with the feature would require less or none components for the external network ... )

---

about TL3472

---

[Eop]

Revised LM308 CLM

comparative test of net-list (macro) against sub-circuit (CLM(component level models))

versus near idealized transitors' CLM (shown@) ↑↓ (see trace Y1)

experimental non-inverting biasing/balancing

DAC from d/s example

---

[Eop]

8-bit ADC experiment

---

Update about component pick

---

[Eop]

500kHz DAC

the 2.5V ref. is provided for possible more exact v. of this -- for example -- forward normalizing the output as Uout=Uin*Vref/(Vsup/2)

Comparative ref. test

Experimental /// Alternative (the best) /// Datasheet (the 2-nd best)

---

it seems that the inverter/comparator type ADC ↓↓ is the fastest here
now with CMOS-Comparators ((i tiled it up intuitively -- a top-down design -- surprisingly or not it came out the same as at the linked one ↑above↑))

(the chosen resistor values may be not the optimal or not the realistic 1-s)

---

[Eop]

yet another DAC

it seems the Spice Models do "Count" -- although this may seem a far shot -- then there is actually a real life analogy or at least a strong potential -- that the certain components or a combination of produces far better results than some others !!

perhaps continued ...

optimistic with "continuous"/slow slope signal

---

[Eop]

4-bit DAC and ADC test

src :: http://www.brown.edu/Departments/Engineering/Courses/En123/Lectures/DAconv.htm

modified

?? -- sounds "fun"

---

best guess :: The Pipelined ADC-s

---

src::not found at web

apx. guess of the ADC circuit layout and biasing resistors

related ::http://chpsndtch.blogspot.com.ee/2017/08/4-bit-adc-improvement.html

base/radix 3 ver. :: uses the same amount of ic-s per cascade -- but has "exponentially" higher resolution

↑ the radix 3 output can be converted to binary by summers -- for example ↑
something similar found at www :: https://www.researchgate.net/publication/220365717_A_Low-Power_Capacitive_Charge_Pump_Based_Pipelined_ADC

---

at the sown  ADC-s when switched to 5V single supply and the CMOS comparators and op amp-s -- the least can be extended with 74HC125 or ↓ 74HC126 ↓ (to gain the OC OE functionality of LM311) . . . in other words by these changes the circuit can be made faster

-

-

-

CMOS Radix-3 :: 2.5x faster than a "slow" LM324

↑ there's some optimistic 2.5µs read window ↑ to stay at the precision of the shown 0 to 26 e.g. 27 level of quantization . . .

---

---

As a target of these tests -- i attempted to find suitable ADC - DAC combination to set up a successive approximation ADC

• as by adding cascades to shown cascaded(/pipelined) ADC-s -- the transition delay to LSB-s increases -- they don't much improve the final conversion speed
• basically the cascaded converters are a "Static SAR DAC" variants -- the SA delay still remains
• i must rethink the concept here
  
  • -- either should use a parallel converter
  • or try to incorporate/integrate a differential approach

---

[Eop]

DAC test

CD4069 outputs are referenced to supply median

checking if such produces a linear ramp . . .
all fun of resolving a simple 3 - supply voltage divider (finding the formula for U_X)

. . . checking if such produces a linear ramp in excel . . .
-- the value 1/2 used in LT Spice seems to be incorrect . . .

---

[Eop]