High noise immunity logic - Update 3

Made some simple comparative "pickup" tests

with the speed --or-- supply range improved variants

. . . and with the original --and-- the biasing adjusted orig.

so far the latest version (A5►Q5) is the least sensitive to (order from most to least susceptible noise source = the INP noise affects the circuit operation the most . . . and the GND noise the least)

• noise from inp
• noise from +power rail
• noise from –power rail

PS! -- don't ignore the switch "so far" -- there is always a test that your equipment will fail at (we just haven't spotted such yet . . . )

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High Noise Immunity Logic - Update 2

When you go round and round improving the circuit you may forget to keep track on some relevant parameters . . . such as the Threshold Voltage and the very Noise Immunity . . . while i improved the speed and the supply range

so - i had to make a new zenerless central threshold variant with reduced speed A5►Q5 below
/// the problem with V_TH being near the one of the rails is that if the rail is noisy it may interfere with low/high threshold level , then again - when the V_TH is near the center the logic may "hang in the middle" or wave around it . . . randomly -- but near the center is more secure from the rail noise

thus - it would be wise to increase the hysteresis . . . but also this has..

• ..a disadvantage in "wave"/signal propagation speed -- as each gate has to complete the hysteresis size transition before the information propagates;
  it must be tested by practice  and decided (oriented to the target application) how much is optimal --or-- least error prone --or-- other
• ..a disadvantage as it adds up to required component count , budget , build time/-space ...

a Falstad Simulation of the oscillator suggests the lower voltage limit to use for OSC. is about 3.5V ? or below → a modified oscillator ← requires a kick start (a RESET in Falstad)

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High Immunity Logic - web circuit mod.

src. ::

Simulated with the zener  and it's substiute

The substitute

Update for wider supply range -- with "doable" alternate for the questionable (6.2V) zener -- questionable as ? does it actually behave as it simulates . . .

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Latest experiments ...

a low voltage DS(hcottky)TL test ::

in :: https://www.falstad.com/circuit/circuitjs.html

in :: https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html

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j-Fet test ::

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scs test (a variety modified from the 7-th ed. GE Transistor Manual 1964) ::

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about :: the following is carried out on intent to find out the low-power-edge function of the scs / pulse-driven logic - - coz there're a lot of old discretes lying around nothing to do with - - in most cases the DTL is out performing such in a sense of power efficiency (but there are few exceptions and some conditional exceptions . . . most yet to be defined . . .)

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(-a-) -- incomplete design of low power HOLD capable RAM/Counter . . .

(-b-) -- i guess the proper operational voltage levels' range selection allows the following to operate without pulse amp stages . . .

(-c-) -- ↓it↓ draws about 10mA per cascade/stage for about 400kHz CLK src. (& takes an additional circuitry to read the trigger OUTP levels . . . e.g. adding even more power use in real implementation . . . )

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another 1.2V DTL variant

trivial random inverter osc. test

2N2222 OUTP , a composite "diode" from 2N2907 1N4148 -- NAND logic
designed for up to 1...2 MHz operation at 1.2V supply
at lesser speeds it can work starting from 620mV supply ...
... which has much no point in practice coz below ??? say 850mV (good battery types) usually 1.13V (most battery types) the terminal voltage drops fast (some minutes even seconds -- tough -- during that some startup circuits can be driven) and deceases -- so below 1.13V (unloaded) terminal voltage the 1.2V battery is basically empty

counters compared XC , JK , Pulse , T

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1.2V Logic revised

I re-tuned most of all of my 1.2V DTL logic designs to function at least in 0.9 to 1.7 V range (using the verification on the first figure of linked post) and run them under the same oscillator setup, updated the past stats. :

 the yellows are the old v.-s of some of the inverters before revision

here're the most time efficient and energy efficient ones :

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Custom eXperimental 0.7 ... 1.9 V DTL

a.k.a. "Math Test" ::

about What?

2N3906 2N3904 1N4147

Speed test ::

for those superstitious* - i don't have time to play ← this ← *game - although there are certain numbers that i like more than some others for example the no. 13 (is a prime number) represents the symmetry turns of the cube (tetra.7 , cube.13 , dodeca.21 = love-sense-wisdom.esoteric.femine : life.?mixed : (over)knowledge-illusion-delirium.male) , 666 = 6 × 111 = (2 × 3) × (3 × 37) ◄ in "my databases" the no 37 syncs with an egypts coat-horned head male "idiot"(read a lower level deity) , the Dim.6.Hi (read the 6-th density high - an upper instance of the 6-th density , it has something you know as a Hi-Devil** (an illusionist - who does not address this world directly) there (there's an oval window to higher/outer space from the doughnut cave he sits the center in - like in the phantom menace near opening scene negotiation room - only all dark/dim inside outside , muhahaa ← the past spirit travel memories) - so the 6 is a place enumerator not the "thing**" ) - you don't generate a new being by simply multiplying the FAR PTR-s (that are - likely-probable-occasional to) near to features - - a creature-spirit is created as a whole ("wave"(-set)-)loop of it's (including the probable possible states of) existence - by multiplying a partial feature pointers to near the feature - or even the whole wave loops - *** you apply a re-definition to a time - your time - of how you preceive those loop-waves - you don't create new time enclosed loop waves (the only beast here is that *** - and even this is too complex for a human to achieve - coz you don't have the variable definitions nor in real time access to - so you only can be afraid of the what if i managed that (? wouldn't it be fun/exciting, ?yes) blak) . . .
. . . whatever here're the speed test results - simulated - in real this particular DTL might not work at all at this supply range or may work a lot of slower coz of all the unidealized features represented . . .

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Had 2 modify smth. i call XC trigger

the test (Update @ MMXVI-02-11 to compare with TTL (SN74xx))

the DTL here is other than in prev. post	X-C 3-ger v. P counter (TTL)
the latches tested	X-C 3-ger (TTL)
L→R , U→D -- pulse-counter , JK-trigger , D-trigger , XC-trigger <•> the pulse-counter uses the pulse-RS-trigger which locks it´s INP and OUTP during transition <•> the XC-trigger uses an adittional state buffer to gain better speed	. . . it seems so far the XC-trigger performs the best of it's kind , if it's implemented correct ??

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about Blogger editor :: using the <dir> tag blunts the editor (in a Compose view) -- it can´t add lines [Shift]+[Enter] correctly -- nor to style text e.g. [Ctrl]-[B] has no effect inside <dir> in Compose view

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a bit unusual logic

was mentioned in pre-prev. post - now i finalized the testing of it - not that it´s ok to go but i just run out the ideas how to futher adjust it . . .

the idea as usual for 1.2V (single battery fed) logic is to make it work at all discharge levels of the battery (1.68V) 1.46V . . . 1.1V(0.75V) -- in common after the battery is discharged below 1.13V it´s power output is limited 4mA continuous drain (10 to 20mA peak loads) and it´s getting worse in minutes - for rechargeable Ni-MH-s the critical voltage is likely lower - that is - they preserve their power output below 1V (unloaded) terminal voltages

 the 1-st run ::


??? still oscillates at 240mV supply ???

Correction: to drop X0 faster usually takes to decrease RC and/or to increase RB

and the 2-nd run ::


tested(read: simulated) at 600mV where the oscillation signal still crosses the threshold
it has 760mV zener that means the supply should be above that level

"XC-trigger" versus JK-trigger - the more idiot proof v. of which is a "pulse-counter" - a pulse-RS-trigger based T rigger
the question here might be  that why to go so complex when the 2-transistor 2-resistor + number of inputs count of diodes do the trick as well . . .
. . . it is that - due the differences in real components - the signal continuity may be lost using simple design
+ the above designs "eat" better the supply and input signal range variations - making it more realistic that i might do something with old SMD transistors "saved" from old blown devices . . .

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Errors induce new knowledge

basically - i was after a while testing a new DTL concept - it was quite a long while - so i didn't exactly recall the threshold test circuit - and due the specific nature of this new DTL the wrong 3-shold circuit started to oscillate ►► reproduced on ancient SN7400

it´s component level model is not the exact thing - but quite close
+ notice the osc. startup forcing . . .

. . . damn i re-opened this post on editor and it there displays correct - here it --

<span style="border-color: red; border-style: solid; border-width: 0 0 1 0;">startup forcing</span>

-- does NOT ????? (?blogger . . . bullsh¡t! -- they have no error here -- it´s someone´s work undone (low budget . . . whatever they don´t have . . .))

+ the RIGHT layout

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1.2V inverter again

The goal :: is to define / design a low power logic for abstract use in powering by "empty" 1.2V batteries

In common the loaded 1.2÷1.5V battery keeps it's terminal voltage above 1.0V , internal resistance - fresh ... "empty" 250÷500mΩ ... 750÷1250mΩ (varies more by battery type and less by manufacturer -- should be measured for specific application)

If the internal resistance goes beyond "1250"mΩ (very apx. value for critical Lim.) it starts rising fast and also the battery's unloaded terminal voltage starts to drop significantly dn2 0.9÷0.8V (◄ below that the battery can be used as - say a 1 minute - to load the capacitor to 550÷770mV and then switch that charge somewhere)

So the secondary use for batteries can be the "central" "dropping voltage" mode - unloaded terminal voltage 1.13 ... 1.0 V output current 20 ... 1mA - thus - the supplied power 23 ... 1.0 mW . . . so if you "define" a mW application such can still work several hours

Back to inverter - the graphs. ::



about ::

• The simulation is verified for 0.9 to 1.9V to be operating as expected
• It is normal to expect for the fast counters not to go over the 1-10th of their simulation frequency
• It is also normal to expect they wont go at any frequency (coz the collector resistance , output load capacity , other ...)
• ... otherwise it'll draw some 14µW at 1.2V U_CC - in other words - ! 1mW supply can push 1000 : 14 = 71 inverters OR 35 RS-triggers (/ D-triggers) OR 12 C-triggers (a 12 stage counter/divider) ►►
• ►► since you have to select the similar-ß BJT-s and to tune 3-shold for each inverter - then - it's impractical to build anything based on components that inverter's TEST prototype here has

▲▲ the entire bullsh¡t is required to pre-calibrate my system before an attenpt to do something with something₂ called "Electric VLSI Design System" -- so as i proceed in an unusual way - the 'log 's provided in case any sub-grid of this insanity 'd B a pt. of interest . . . 3,2,1,OFF

Unverified

that the following would EXIST
....
(waiting the 'logger & FF becoming responsive)
....
(still waiting)
...

..
(still waiting)
...

^{((◄◄restored apx. as it was))}

while those booster diodes might do the trick - the design wont work on voluntary diodes - especially those labelled on figure coz the high ohmic collector load wont be enough in real life to lock the input diodes (or lock 'em fast) e.g. the inverters won't work at all or would work 10-s of times slower than the simulation does F;i yoo-hoo . . . everything may work better if you rise the feed voltage above ?? 1.85V 2.0V 2.16V or higher ?? (the dif.-amp starts working properly above-equal 9.6V . . .)

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DTL logic visualised

just wanted to see D-trigger in operation - is a 6 stage module - only made 2 so far - enough for the RS trigger

<iframe allowfullscreen="" frameborder="0" height="480" src="//www.youtube.com/embed/Nwg2JhP_rYc" width="640">
<!-- (embbed you arse) - another bulls'that causes blogger to hang F! . . . //-->

"WYSIWYG" . . . apx. -- the schematic

 PLOT

 TIMED to apx. match the video

B4 proceeding the 3-rd stage must assembled - each instance must be parametrized for continuity of discreet signal flow - if such is continuous and we get some oscillator running then it's enough to give it a GO - t.m. - the PCB must designed , made , perhaps some sh¡t more - then we run the visualization test - and the resource becomes a spare parts again - t.m. - design a PCB so the components are least affected - really annoying stuff that can be done if you have nothing else to do or need to test some new feature ...
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