When you go round and round improving the circuit you may forget to keep track on some relevant parameters . . . such as the Threshold Voltage and the very Noise Immunity . . . while i improved the speed and the supply range
so - i had to make a new zenerless central threshold variant with reduced speed A5►Q5 below
/// the problem with VTH being near the one of the rails is that if the rail is noisy it may interfere with low/high threshold level , then again - when the VTH is near the center the logic may "hang in the middle" or wave around it . . . randomly -- but near the center is more secure from the rail noise
thus - it would be wise to increase the hysteresis . . . but also this has..
a Falstad Simulation of the oscillator suggests the lower voltage limit to use for OSC. is about 3.5V ? or below → a modified oscillator ← requires a kick start (a RESET in Falstad)
[Eop]
so - i had to make a new zenerless central threshold variant with reduced speed A5►Q5 below
/// the problem with VTH being near the one of the rails is that if the rail is noisy it may interfere with low/high threshold level , then again - when the VTH is near the center the logic may "hang in the middle" or wave around it . . . randomly -- but near the center is more secure from the rail noise
thus - it would be wise to increase the hysteresis . . . but also this has..
- ..a disadvantage in "wave"/signal propagation speed -- as each gate has to complete the hysteresis size transition before the information propagates;
it must be tested by practice and decided (oriented to the target application) how much is optimal --or-- least error prone --or-- other - ..a disadvantage as it adds up to required component count , budget , build time/-space ...
a Falstad Simulation of the oscillator suggests the lower voltage limit to use for OSC. is about 3.5V ? or below → a modified oscillator ← requires a kick start (a RESET in Falstad)
[Eop]
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