Friday, September 13, 2019

the 2-nd compile of the "Low Power Pulse Generator"

trivial warm-up test

a high power (an inefficient pulse generator)

a low power (an efficient pulse generator)

. . . optimizing for wider range of R4

. . . optimizing for component count


Monday, August 26, 2019

Another LTSpice Bug

curiously the bug is identical as in the LTspiceIV v. 4.23l as also in the LTspiceXVII v. XVII

Late update : a Yahoo group discussion log - copy -- basically it turned out to be an exceptional.. (in practice but) trivial (by functionality described in "documentation" ← if there is such) ..behaviour of the LTSpice simulation engine . . . where the simulator can't decide whether there is any activity in circuit (although it is obvious for human that there is . . . insane -- but there are even more stupid "computer bugs" in IT -- it's just "another one such" . . .)

in images ::


Thursday, July 18, 2019

ADC variant using the OC outp mod from the prev. post

lately , in conjunction with the other work , i noticed that the software ADC , i fast wrote for one of the experiments , actually can be implemented pretty much "as is" and on the real components ...

here's the ADC variant (the only problem will be to keep the voltages steady enough that the output would ... exist ! ...)

in above the voltages Vr0 to Vr3 (near) match the voltages Q1 to Q4 (the least being generated by the hw implementation of the ADC)

the fascinating thing is the relative simplicity of it (although the single chip DAC or µC with the feature would require less or none components for the external network ... )

about TL3472


Monday, June 17, 2019

OC OD output voltage divider calculator

Voltage Divider - Calculator

Param. Input Set Value Verif.
Corr. : .
ISNK : .
VCC : .
VTH : .
ΔV : .
UHI = VTH + ΔV :
ULO = VTH - ΔV :
Integrity of the entered data :
R3 (Ω) = ROC = RSNK : .. .
K = R2/R0 = :
= VCC / ULO - 1
VCC / UHI - 1
R2 (Ω) = RLO =
= R3 · ( K - 1 ) :
.. .
R0 = R2||R3 : ...
R1 (Ω) = RHI : .. .


Sunday, June 16, 2019

Determining a near to the exact HFE value

Not providing how did we got there -- the IC IE are best to be kept below-equal to the 1.5mA and less

more ::

utilities ::


Friday, June 14, 2019

Bipolar Passgate Experiment

There are obviously more tests to be done to evaluate the thing . . . but so far there are 2 of them :

resistive load + sample and hold ::


Saturday, April 27, 2019

Cap.-meter core by target type



both types need possible additional timing or/and displaying(+conversion4) circuitry -- that is not at the scope of this post - - - - we only examine the possible to achieve precision here


Friday, April 12, 2019

Confirming the web cap-meter principle

the thing is theoretically capable of more precise function that it's claimed but in practice . . . i don't think it can do even twice the claimed 4%

. . . there are 3 to 6 constants that have to be set correct at the 10-th of a % precision -- but they are valid at a specific device working temperature + don't with-count / cancel-out the variation of parasitic properties of different capacitors

experiment ::

the diodes have a logarithmic voltage --or-- apx. Δi.D ~ exp(U.D) ... also the ΔU.c ~ exp(t) ...
... thus Δi.D ~ exp(exp(t)) --or-- if the U.c rises the frequency (Δi.D) must rise exponentially to provide ?? more linear U.c scale → the meter should run at constant outp voltage and varing frequency (4 starting ...)


Thursday, April 11, 2019

Latest experiments ...

a low voltage DS(hcottky)TL test ::

in ::

in ::

j-Fet test ::

scs test (a variety modified from the 7-th ed. GE Transistor Manual 1964) ::

about :: the following is carried out on intent to find out the low-power-edge function of the scs / pulse-driven logic - - coz there're a lot of old discretes lying around nothing to do with - - in most cases the DTL is out performing such in a sense of power efficiency (but there are few exceptions and some conditional exceptions . . . most yet to be defined . . .)

(-a-) -- incomplete design of low power HOLD capable RAM/Counter . . .

(-b-) -- i guess the proper operational voltage levels' range selection allows the following to operate without pulse amp stages . . .

(-c-) -- ↓it↓ draws about 10mA per cascade/stage for about 400kHz CLK src. (& takes an additional circuitry to read the trigger OUTP levels . . . e.g. adding even more power use in real implementation . . . )


Saturday, April 6, 2019

BjT versus OpAmp Staircase Generator

src::GE Transistor Manual 7-th ed. 1964 p.345
about :: it takes higher energy pulses + a NEG supply to run , (it may be not so as i quite don't get yet the anatomy of the thing but) it seems to have a worse linearity than the OpAmp v. though it also seems to keep it's levels longer in place and have a smaller variation in step size near zero to near Vcc (to "Zero the drift" it takes somewhat unreal precision tuning of the bias resistors . . . )

PS! -- The RESET circuitry is NOT implemented for neither one of the gen.-s -- coz it'd result in slower simulation times - and it should be relatively easy to set up one for your needs
. . . also the use of low power oscillator requires a buffer 1 to not be affected from the fast-/"a low resistance value" -biasing resistors' reaction/(?bwd coupling)

src:: (Fig.28)
about :: the OpAmp v. accepts a higher variety of pulse voltages and tank-/integrator capacitor values -- the linearity is likely better than for bjt v. also the integration range is bigger (due lesser possible pulse amplitude values and the possibility to drive OUTP (Vsc) more close to upper rail . . .)


Tuesday, March 26, 2019

Testing Pseudo Capacitors

it turns out you can cook a lot of capacities out of bipolar triode

a descending list :: (also on the 1-st fig. below)
  • connect E2E2C2C using bases as outputs or (equals) tie E&C together and merge B-s
  • connect E2E & C2C using bases as outputs
  • connect E2C & C2E using bases as outputs
  • tie CB-s together and use as outputs merge by E-s
  • tie EB-s together and use as outputs merge by C-s
(PS! -- the shown voltage tuning takes up to about a second to settle !!!)

+ a simple osc. test ::


Tuesday, March 19, 2019


LM393 speed test with a dynamic output voltage divider -- gives a best high speed sense range for the 5V supply

the divider (conditionally --and/or-- very approximately ) corresponds to about a single 3.6kΩ pullup resistor (or speculatively to about 1mA max. sink current at high frequency = (5 - 1.4)·1V/3.6kΩ)

An experimental javaScript Output Voltage Divider Calculator

Voltage Divider - Calculator

The Browser Detected ... : : : : : : (about guessing the Browser) :
Integrity of the entered data :
R1 :
R2 :
R3 :
R0 : -- R0 = R1||R3

Usage :: R1 to R3 correspond to {r1} to {r3} on the Fig. above

Summing it up ::


Monday, March 18, 2019

Log./Antilog. TEST

pay attention to the formulas in plot pane


Sunday, March 17, 2019

LM324 versus LM308 -- MM versus CLM

LM324 versus LM308 -- Macro Model versus Component Level Model

In small signal range the LM308 (an older design 1969) seems to have a half faster response than the LM324 (a newer design ?1972?)

signal shape dependency on input amplitude ::

the particular apx.-n of LM324 CLM is not too exact (but in some tests shows out a better performance than it's factory provided macro- (a "net list" .cir) model)


Thursday, March 14, 2019

Progressive current limiting

Figures ::

Legend :: opamp.Q1 mirrors the current at R5 , opamp.Q2 limits the current progressively ... and incase of the SC it cuts the output the more off the lower is the output voltage -- so there's double level progressive limiting (the fig.2 shows the 1-st and the fig.-s 3 to 5 show the 2-nd - a short circuit - limiting levels) . . . the resistor values for R24 to R26 and R21 , R22 , also for the R14 may need to be adjusted to get the real build of the circuit stable (maybe it takes more adjustments -- but these are known to be more likely critical at this stage of dev.)