Reviewed an old concept - came out wit a new one . . .
in the follofing the timescale shows the actual time . . .
[Eop]
in the follofing the timescale shows the actual time . . .
[Eop]
Wednesday, December 18, 2019
Saturday, November 23, 2019
Comparing TTL JK Triggers' Logic Designs
There was recently needed a realistic JK Simulation for which i had to set up one coz the Spice has no built in version . . . so i compared the equivalent circuits at d/s-s and made few additional 1-s.
It turned out that at high speed some perform more accurate than the others
From d/s - the only good one was 74LS73 , from custom 1-s - 2 became out credible : a mod of '7474 into JK --and-- a "self-confirming" JK -- that was made to have a least error JK to compare others against . . .
In the moderate/high speeds all perform correct
The variations occur near the speed limit
+ The last two compared ...
[Eop]
It turned out that at high speed some perform more accurate than the others
From d/s - the only good one was 74LS73 , from custom 1-s - 2 became out credible : a mod of '7474 into JK --and-- a "self-confirming" JK -- that was made to have a least error JK to compare others against . . .
In the moderate/high speeds all perform correct
The variations occur near the speed limit
+ The last two compared ...
[Eop]
Monday, November 18, 2019
High noise immunity logic - Update 3
Made some simple comparative "pickup" tests
with the speed --or-- supply range improved variants
. . . and with the original --and-- the biasing adjusted orig.
so far the latest version (A5►Q5) is the least sensitive to (order from most to least susceptible noise source = the INP noise affects the circuit operation the most . . . and the GND noise the least)
[Eop]
with the speed --or-- supply range improved variants
. . . and with the original --and-- the biasing adjusted orig.
so far the latest version (A5►Q5) is the least sensitive to (order from most to least susceptible noise source = the INP noise affects the circuit operation the most . . . and the GND noise the least)
- noise from inp
- noise from +power rail
- noise from –power rail
[Eop]
Sunday, November 17, 2019
High Noise Immunity Logic - Update 2
When you go round and round improving the circuit you may forget to keep track on some relevant parameters . . . such as the Threshold Voltage and the very Noise Immunity . . . while i improved the speed and the supply range
so - i had to make a new zenerless central threshold variant with reduced speed A5►Q5 below
/// the problem with VTH being near the one of the rails is that if the rail is noisy it may interfere with low/high threshold level , then again - when the VTH is near the center the logic may "hang in the middle" or wave around it . . . randomly -- but near the center is more secure from the rail noise
thus - it would be wise to increase the hysteresis . . . but also this has..
a Falstad Simulation of the oscillator suggests the lower voltage limit to use for OSC. is about 3.5V ? or below → a modified oscillator ← requires a kick start (a RESET in Falstad)
[Eop]
so - i had to make a new zenerless central threshold variant with reduced speed A5►Q5 below
/// the problem with VTH being near the one of the rails is that if the rail is noisy it may interfere with low/high threshold level , then again - when the VTH is near the center the logic may "hang in the middle" or wave around it . . . randomly -- but near the center is more secure from the rail noise
thus - it would be wise to increase the hysteresis . . . but also this has..
- ..a disadvantage in "wave"/signal propagation speed -- as each gate has to complete the hysteresis size transition before the information propagates;
it must be tested by practice and decided (oriented to the target application) how much is optimal --or-- least error prone --or-- other - ..a disadvantage as it adds up to required component count , budget , build time/-space ...
a Falstad Simulation of the oscillator suggests the lower voltage limit to use for OSC. is about 3.5V ? or below → a modified oscillator ← requires a kick start (a RESET in Falstad)
[Eop]
Thursday, November 14, 2019
High Immunity Logic - web circuit mod.
src. ::
Simulated with the zener and it's substiute
The substitute
Update for wider supply range -- with "doable" alternate for the questionable (6.2V) zener -- questionable as ? does it actually behave as it simulates . . .
[Eop]
Simulated with the zener and it's substiute
The substitute
Update for wider supply range -- with "doable" alternate for the questionable (6.2V) zener -- questionable as ? does it actually behave as it simulates . . .
[Eop]
Friday, September 13, 2019
the 2-nd compile of the "Low Power Pulse Generator"
trivial warm-up test
a high power (an inefficient pulse generator)
a low power (an efficient pulse generator)
. . . optimizing for wider range of R4
. . . optimizing for component count
[Eop]
a high power (an inefficient pulse generator)
a low power (an efficient pulse generator)
. . . optimizing for wider range of R4
. . . optimizing for component count
[Eop]
Monday, August 26, 2019
Another LTSpice Bug
curiously the bug is identical as in the LTspiceIV v. 4.23l as also in the LTspiceXVII v. XVII
Late update : a Yahoo group discussion log - copy -- basically it turned out to be an exceptional.. (in practice but) trivial (by functionality described in "documentation" ← if there is such) ..behaviour of the LTSpice simulation engine . . . where the simulator can't decide whether there is any activity in circuit (although it is obvious for human that there is . . . insane -- but there are even more stupid "computer bugs" in IT -- it's just "another one such" . . .)
in images ::
[Eop]
Late update : a Yahoo group discussion log - copy -- basically it turned out to be an exceptional.. (in practice but) trivial (by functionality described in "documentation" ← if there is such) ..behaviour of the LTSpice simulation engine . . . where the simulator can't decide whether there is any activity in circuit (although it is obvious for human that there is . . . insane -- but there are even more stupid "computer bugs" in IT -- it's just "another one such" . . .)
in images ::
[Eop]
Thursday, July 18, 2019
ADC variant using the OC outp mod from the prev. post
lately , in conjunction with the other work , i noticed that the software ADC , i fast wrote for one of the experiments , actually can be implemented pretty much "as is" and on the real components ...
here's the ADC variant (the only problem will be to keep the voltages steady enough that the output would ... exist ! ...)
in above the voltages Vr0 to Vr3 (near) match the voltages Q1 to Q4 (the least being generated by the hw implementation of the ADC)
the fascinating thing is the relative simplicity of it (although the single chip DAC or µC with the feature would require less or none components for the external network ... )
about TL3472
[Eop]
here's the ADC variant (the only problem will be to keep the voltages steady enough that the output would ... exist ! ...)
in above the voltages Vr0 to Vr3 (near) match the voltages Q1 to Q4 (the least being generated by the hw implementation of the ADC)
the fascinating thing is the relative simplicity of it (although the single chip DAC or µC with the feature would require less or none components for the external network ... )
about TL3472
[Eop]
Monday, June 17, 2019
OC OD output voltage divider calculator
extends the :: LM393 CLM TEST @ Tuesday, March 19, 2019
Voltage Divider - Calculator
| Param. | Input | Set | Value | Verif. | |||||
|---|---|---|---|---|---|---|---|---|---|
| Corr. : | . | ||||||||
| ISNK : | . | ||||||||
| VCC : | . | ||||||||
| VTH : | . | ||||||||
| ΔV : | . | ||||||||
| UHI = VTH + ΔV : | |||||||||
| ULO = VTH - ΔV : | |||||||||
| Integrity of the entered data : | |||||||||
| R3 (Ω) = ROC = RSNK : | . | . | . | ||||||
|
. | . | |||||||
| R2 (Ω) = RLO = = R3 · ( K - 1 ) : | . | . | . | ||||||
| R0 = R2||R3 : | . | . | . | ||||||
| R1 (Ω) = RHI : | . | . | . | ||||||
[Eop]
Sunday, June 16, 2019
Determining a near to the exact HFE value
Not providing how did we got there -- the IC IE are best to be kept below-equal to the 1.5mA and less
more ::
utilities ::
[Eop]
more ::
utilities ::
[Eop]
Friday, June 14, 2019
Bipolar Passgate Experiment
There are obviously more tests to be done to evaluate the thing . . . but so far there are 2 of them :
resistive load + sample and hold ::
[Eop]
resistive load + sample and hold ::
[Eop]
Saturday, April 27, 2019
Cap.-meter core by target type
"ceramic"
"polar"
both types need possible additional timing or/and displaying(+conversion4) circuitry -- that is not at the scope of this post - - - - we only examine the possible to achieve precision here
[Eop]
"polar"
both types need possible additional timing or/and displaying(+conversion4) circuitry -- that is not at the scope of this post - - - - we only examine the possible to achieve precision here
[Eop]
Friday, April 12, 2019
Confirming the web cap-meter principle
the thing is theoretically capable of more precise function that it's claimed but in practice . . . i don't think it can do even twice the claimed 4%
. . . there are 3 to 6 constants that have to be set correct at the 10-th of a % precision -- but they are valid at a specific device working temperature + don't with-count / cancel-out the variation of parasitic properties of different capacitors
experiment ::
the diodes have a logarithmic voltage --or-- apx. Δi.D ~ exp(U.D) ... also the ΔU.c ~ exp(t) ...
... thus Δi.D ~ exp(exp(t)) --or-- if the U.c rises the frequency (Δi.D) must rise exponentially to provide ?? more linear U.c scale → the meter should run at constant outp voltage and varing frequency (4 starting ...)
[Eop]
. . . there are 3 to 6 constants that have to be set correct at the 10-th of a % precision -- but they are valid at a specific device working temperature + don't with-count / cancel-out the variation of parasitic properties of different capacitors
experiment ::
the diodes have a logarithmic voltage --or-- apx. Δi.D ~ exp(U.D) ... also the ΔU.c ~ exp(t) ...
... thus Δi.D ~ exp(exp(t)) --or-- if the U.c rises the frequency (Δi.D) must rise exponentially to provide ?? more linear U.c scale → the meter should run at constant outp voltage and varing frequency (4 starting ...)
[Eop]
Thursday, April 11, 2019
Latest experiments ...
a low voltage DS(hcottky)TL test ::
in :: https://www.falstad.com/circuit/circuitjs.html
in :: https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html
j-Fet test ::
scs test (a variety modified from the 7-th ed. GE Transistor Manual 1964) ::
about :: the following is carried out on intent to find out the low-power-edge function of the scs / pulse-driven logic - - coz there're a lot of old discretes lying around nothing to do with - - in most cases the DTL is out performing such in a sense of power efficiency (but there are few exceptions and some conditional exceptions . . . most yet to be defined . . .)
(-a-) -- incomplete design of low power HOLD capable RAM/Counter . . .
(-b-) -- i guess the proper operational voltage levels' range selection allows the following to operate without pulse amp stages . . .
(-c-) -- ↓it↓ draws about 10mA per cascade/stage for about 400kHz CLK src. (& takes an additional circuitry to read the trigger OUTP levels . . . e.g. adding even more power use in real implementation . . . )
[Eop]
in :: https://www.falstad.com/circuit/circuitjs.html
in :: https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html
j-Fet test ::
scs test (a variety modified from the 7-th ed. GE Transistor Manual 1964) ::
about :: the following is carried out on intent to find out the low-power-edge function of the scs / pulse-driven logic - - coz there're a lot of old discretes lying around nothing to do with - - in most cases the DTL is out performing such in a sense of power efficiency (but there are few exceptions and some conditional exceptions . . . most yet to be defined . . .)
(-a-) -- incomplete design of low power HOLD capable RAM/Counter . . .
(-b-) -- i guess the proper operational voltage levels' range selection allows the following to operate without pulse amp stages . . .
(-c-) -- ↓it↓ draws about 10mA per cascade/stage for about 400kHz CLK src. (& takes an additional circuitry to read the trigger OUTP levels . . . e.g. adding even more power use in real implementation . . . )
[Eop]
Saturday, April 6, 2019
BjT versus OpAmp Staircase Generator
src::GE Transistor Manual 7-th ed. 1964 p.345
about :: it takes higher energy pulses + a NEG supply to run , (it may be not so as i quite don't get yet the anatomy of the thing but) it seems to have a worse linearity than the OpAmp v. though it also seems to keep it's levels longer in place and have a smaller variation in step size near zero to near Vcc (to "Zero the drift" it takes somewhat unreal precision tuning of the bias resistors . . . )
PS! -- The RESET circuitry is NOT implemented for neither one of the gen.-s -- coz it'd result in slower simulation times - and it should be relatively easy to set up one for your needs
. . . also the use of low power oscillator requires a buffer 1 to not be affected from the fast-/"a low resistance value" -biasing resistors' reaction/(?bwd coupling)
src::http://zpostbox.ru/g4_e.htm (Fig.28)
about :: the OpAmp v. accepts a higher variety of pulse voltages and tank-/integrator capacitor values -- the linearity is likely better than for bjt v. also the integration range is bigger (due lesser possible pulse amplitude values and the possibility to drive OUTP (Vsc) more close to upper rail . . .)
[Eop]
about :: it takes higher energy pulses + a NEG supply to run , (it may be not so as i quite don't get yet the anatomy of the thing but) it seems to have a worse linearity than the OpAmp v. though it also seems to keep it's levels longer in place and have a smaller variation in step size near zero to near Vcc (to "Zero the drift" it takes somewhat unreal precision tuning of the bias resistors . . . )
PS! -- The RESET circuitry is NOT implemented for neither one of the gen.-s -- coz it'd result in slower simulation times - and it should be relatively easy to set up one for your needs
. . . also the use of low power oscillator requires a buffer 1 to not be affected from the fast-/"a low resistance value" -biasing resistors' reaction/(?bwd coupling)
src::http://zpostbox.ru/g4_e.htm (Fig.28)
about :: the OpAmp v. accepts a higher variety of pulse voltages and tank-/integrator capacitor values -- the linearity is likely better than for bjt v. also the integration range is bigger (due lesser possible pulse amplitude values and the possibility to drive OUTP (Vsc) more close to upper rail . . .)
[Eop]