Saturday, April 27, 2019

Cap.-meter core by target type



both types need possible additional timing or/and displaying(+conversion4) circuitry -- that is not at the scope of this post - - - - we only examine the possible to achieve precision here


Friday, April 12, 2019

Confirming the web cap-meter principle

the thing is theoretically capable of more precise function that it's claimed but in practice . . . i don't think it can do even twice the claimed 4%

. . . there are 3 to 6 constants that have to be set correct at the 10-th of a % precision -- but they are valid at a specific device working temperature + don't with-count / cancel-out the variation of parasitic properties of different capacitors

experiment ::

the diodes have a logarithmic voltage --or-- apx. Δi.D ~ exp(U.D) ... also the ΔU.c ~ exp(t) ...
... thus Δi.D ~ exp(exp(t)) --or-- if the U.c rises the frequency (Δi.D) must rise exponentially to provide ?? more linear U.c scale → the meter should run at constant outp voltage and varing frequency (4 starting ...)


Thursday, April 11, 2019

Latest experiments ...

a low voltage DS(hcottky)TL test ::

in ::

in ::

j-Fet test ::

scs test (a variety modified from the 7-th ed. GE Transistor Manual 1964) ::

about :: the following is carried out on intent to find out the low-power-edge function of the scs / pulse-driven logic - - coz there're a lot of old discretes lying around nothing to do with - - in most cases the DTL is out performing such in a sense of power efficiency (but there are few exceptions and some conditional exceptions . . . most yet to be defined . . .)

(-a-) -- incomplete design of low power HOLD capable RAM/Counter . . .

(-b-) -- i guess the proper operational voltage levels' range selection allows the following to operate without pulse amp stages . . .

(-c-) -- ↓it↓ draws about 10mA per cascade/stage for about 400kHz CLK src. (& takes an additional circuitry to read the trigger OUTP levels . . . e.g. adding even more power use in real implementation . . . )


Saturday, April 6, 2019

BjT versus OpAmp Staircase Generator

src::GE Transistor Manual 7-th ed. 1964 p.345
about :: it takes higher energy pulses + a NEG supply to run , (it may be not so as i quite don't get yet the anatomy of the thing but) it seems to have a worse linearity than the OpAmp v. though it also seems to keep it's levels longer in place and have a smaller variation in step size near zero to near Vcc (to "Zero the drift" it takes somewhat unreal precision tuning of the bias resistors . . . )

PS! -- The RESET circuitry is NOT implemented for neither one of the gen.-s -- coz it'd result in slower simulation times - and it should be relatively easy to set up one for your needs
. . . also the use of low power oscillator requires a buffer 1 to not be affected from the fast-/"a low resistance value" -biasing resistors' reaction/(?bwd coupling)

src:: (Fig.28)
about :: the OpAmp v. accepts a higher variety of pulse voltages and tank-/integrator capacitor values -- the linearity is likely better than for bjt v. also the integration range is bigger (due lesser possible pulse amplitude values and the possibility to drive OUTP (Vsc) more close to upper rail . . .)


Tuesday, March 26, 2019

Testing Pseudo Capacitors

it turns out you can cook a lot of capacities out of bipolar triode

a descending list :: (also on the 1-st fig. below)
  • connect E2E2C2C using bases as outputs or (equals) tie E&C together and merge B-s
  • connect E2E & C2C using bases as outputs
  • connect E2C & C2E using bases as outputs
  • tie CB-s together and use as outputs merge by E-s
  • tie EB-s together and use as outputs merge by C-s
(PS! -- the shown voltage tuning takes up to about a second to settle !!!)

+ a simple osc. test ::


Tuesday, March 19, 2019


LM393 speed test with a dynamic output voltage divider -- gives a best high speed sense range for the 5V supply

the divider (conditionally --and/or-- very approximately ) corresponds to about a single 3.6kΩ pullup resistor (or speculatively to about 1mA max. sink current at high frequency = (5 - 1.4)·1V/3.6kΩ)

An experimental javaScript Output Voltage Divider Calculator

Voltage Divider - Calculator

The Browser Detected ... : : : : : : (about guessing the Browser) :
Integrity of the entered data :
R1 :
R2 :
R3 :
R0 : -- R0 = R1||R3

Usage :: R1 to R3 correspond to {r1} to {r3} on the Fig. above

Summing it up ::


Monday, March 18, 2019

Log./Antilog. TEST

pay attention to the formulas in plot pane


Sunday, March 17, 2019

LM324 versus LM308 -- MM versus CLM

LM324 versus LM308 -- Macro Model versus Component Level Model

In small signal range the LM308 (an older design 1969) seems to have a half faster response than the LM324 (a newer design ?1972?)

signal shape dependency on input amplitude ::

the particular apx.-n of LM324 CLM is not too exact (but in some tests shows out a better performance than it's factory provided macro- (a "net list" .cir) model)


Thursday, March 14, 2019

Progressive current limiting

Figures ::

Legend :: opamp.Q1 mirrors the current at R5 , opamp.Q2 limits the current progressively ... and incase of the SC it cuts the output the more off the lower is the output voltage -- so there's double level progressive limiting (the fig.2 shows the 1-st and the fig.-s 3 to 5 show the 2-nd - a short circuit - limiting levels) . . . the resistor values for R24 to R26 and R21 , R22 , also for the R14 may need to be adjusted to get the real build of the circuit stable (maybe it takes more adjustments -- but these are known to be more likely critical at this stage of dev.)


Saturday, March 9, 2019

Revised LM308 CLM

comparative test of net-list (macro) against sub-circuit (CLM(component level models))

versus near idealized transitors' CLM (shown@) ↑↓ (see trace Y1)

experimental non-inverting biasing/balancing

DAC from d/s example


Saturday, February 23, 2019

revised my LM393 CLM-s

using two types of test ::

about ::


Friday, February 22, 2019

32kHz X-tal osc -- new variants

12µA Bjt v. ::

2µA j-Fet v. ::

see also an old C-MOS inverter variant :


Friday, February 15, 2019

Q.C. the DAC7822 concept

the non-neg. (bi-polar) multiplication wiring gave the better performance in the sense of speed


Tuesday, February 5, 2019

LM710 from d/s

the previous attempt to make it work (just by principal schematic) failed ... from d/s the magical hFE seems to be 11 . . . ??? (as it's the same timer as 54x00 74x00 series -- the gained information may be practical in getting these models to work with the d/s specified resistances . . .)

my input sensitivity is a bit poorer than the К554СА2 documentation specifies , but basically it will do

note :: even if it takes dual supply and more power than new comparators - then it usually is up to 10 times cheaper for experimental circuits - and someone still may have a storefull of them . . .

the hFE is not matching the 74x00 series

the pages 7,8 have a scope diagram for comparator compared to TTL inverter ::

Reproduced experiment ??? ::


random Op Amp Gain adjustment method (slow -- not optimal delay)

i thought it was easy* but (i usually don't compute things unless i have to) when i wrote up a formula it turned out not as such

anyways seems to work without major problems from gain 2 to 8

note* :: that the GA would equal 1+1/gain (as infact it's GA = 1 1 - 2 Gain )

about ::

Thursday, January 17, 2019

Lo-Vo VCO dev. (prev. follow-up)

the ?? std. ?? VCO from LM139 d/s does not perform too good nor stable.fnOf(control voltage)

so needed to retail one for 3.3V ...

... in prior of what picking the Op Amp model capable for this task was essential

. . . & the result ordered by relative change in frequency ::

In "practice" the controls eat off much like half the power -- e.g. -- the LED-s need to be multiplied by the factor of 10x to get the normal efficiency out of it --or-- the controls need to be replaced by the lower power ones . . . a tricky part . . . also (in case of increasing the number of LED-s) it requires more battery power so the step up conversion is a better approach (and more efficient and easier to control by default)