The goal :: is to define / design a low power logic for abstract use in powering by "empty" 1.2V batteries
In common the loaded 1.2÷1.5V battery keeps it's terminal voltage above 1.0V , internal resistance - fresh ... "empty" 250÷500mΩ ... 750÷1250mΩ (varies more by battery type and less by manufacturer -- should be measured for specific application)
If the internal resistance goes beyond "1250"mΩ (very apx. value for critical Lim.) it starts rising fast and also the battery's unloaded terminal voltage starts to drop significantly dn2 0.9÷0.8V (◄ below that the battery can be used as - say a 1 minute - to load the capacitor to 550÷770mV and then switch that charge somewhere)
So the secondary use for batteries can be the "central" "dropping voltage" mode - unloaded terminal voltage 1.13 ... 1.0 V output current 20 ... 1mA - thus - the supplied power 23 ... 1.0 mW . . . so if you "define" a mW application such can still work several hours
Back to inverter - the graphs. ::
about ::
▲▲ the entire bullsh¡t is required to pre-calibrate my system before an attenpt to do something with something2 called "Electric VLSI Design System" -- so as i proceed in an unusual way - the 'log 's provided in case any sub-grid of this insanity 'd B a pt. of interest . . . 3,2,1,OFF
In common the loaded 1.2÷1.5V battery keeps it's terminal voltage above 1.0V , internal resistance - fresh ... "empty" 250÷500mΩ ... 750÷1250mΩ (varies more by battery type and less by manufacturer -- should be measured for specific application)
If the internal resistance goes beyond "1250"mΩ (very apx. value for critical Lim.) it starts rising fast and also the battery's unloaded terminal voltage starts to drop significantly dn2 0.9÷0.8V (◄ below that the battery can be used as - say a 1 minute - to load the capacitor to 550÷770mV and then switch that charge somewhere)
So the secondary use for batteries can be the "central" "dropping voltage" mode - unloaded terminal voltage 1.13 ... 1.0 V output current 20 ... 1mA - thus - the supplied power 23 ... 1.0 mW . . . so if you "define" a mW application such can still work several hours
Back to inverter - the graphs. ::
about ::
- The simulation is verified for 0.9 to 1.9V to be operating as expected
- It is normal to expect for the fast counters not to go over the 1-10th of their simulation frequency
- It is also normal to expect they wont go at any frequency (coz the collector resistance , output load capacity , other ...)
- ... otherwise it'll draw some 14µW at 1.2V UCC - in other words - ! 1mW supply can push 1000 : 14 = 71 inverters OR 35 RS-triggers (/ D-triggers) OR 12 C-triggers (a 12 stage counter/divider) ►►
- ►► since you have to select the similar-ß BJT-s and to tune 3-shold for each inverter - then - it's impractical to build anything based on components that inverter's TEST prototype here has
▲▲ the entire bullsh¡t is required to pre-calibrate my system before an attenpt to do something with something2 called "Electric VLSI Design System" -- so as i proceed in an unusual way - the 'log 's provided in case any sub-grid of this insanity 'd B a pt. of interest . . . 3,2,1,OFF
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