. . . integrated the www resource (poor) with my past experimental Lo voltage SCS designs . . . to just about get a working theoretical "New One" -- the 2 things marked on a fig. tell us that such is not likely to succeed in practice ...
actually i was playing around with oscillator designs the SCS-s in mind -- the cool feature about this thing (scs) is like some modern GHz MOSFET counters also DRAM e.c. those things can be designed to use practically no current and then shift 'em to another state by a narrow pulse
so, while i achieved my next osc. i studied in parallel an old electronics book - came across with ?? neg. triggered ring counter ?? thought to investigate it , improved the "CLK" shown in book for 1.2V supply . . .
after no success with the counter i actually realized that the TYPE of a counter i'm using for my improved CLK uses the pos. going pulse . . . yo!
. . . usually i finish what i started so the 1.fig. of this post actually shows the finished 1.2V design
for incase i'd ever need such in practice - i converted it to higher vtg. v. where the SCS is more likely to operate in realistic supply range . . . -- the ▼ "signal forward continuity test" ▼
► what's it made of ▼▼
it's tricky to get the signal out from low power "oscillators" -- here's one possibility :
PS! -- as the simulation in Spice may perform up to 1000x better than the actual circuit in real then it's not recommended to rush blindly building large systems composing them from the unknown / not studied designs
-- it's about 1 to 1k x that averages to ²√(1·1000) = 30dB = apx. 32x in general (more usually it's about 10x - maybe coz i ban the designs that perform worse ...) -- to get this right -- say if your 10Vdc PSU design has a simulation peak error ±24µV then in real device the appropriate value is to be expected ±24mV -- so it's 1000x change in relative error . . . as ±24mV/10V is ±0.24% then the common understanding of 1k x performance drop can't be grasped right without knowing the preceesding
-- it's also why i don't build much of the stuff -- coz it takes testing separate stages . . . 1 by 1 . . . also verifying similar (same circuit) stages built from real components (with deviating parameters) that usually ends up in narrowing the operating ranges . . . without all possible fancy lab equipment in hand it takes more time than there is available . . .
... e.g. if you find such (SCS counter) interesting you have to perform further development-testing with (/based on) the real components you have in hand for such . . . before attempting to integrate it to any larger application !!!