at this point i am likely able to design better of any type of these xTL stages however there are some things that came out in prev. studies::
1) the simple TTL NAND (up right) supports higer frequencies but only up to 3-4 input gates
2) the CMOS type gates (lowwer right) consist of "too many" components
3) the best power_draw : component_count : input_count : MHz_per_unit_Power is top left
Stats:
what is being marked here is exceptional to studied set designs - lets take a closer look:
is the highest frequency v. of the exceptions a TTL stage based on 2N5087 (good sensitivity at low power) as the exceptional performance is due to the performance of that transistor drawing in average 130µA/stg.
the 2-nd fast exception being tested for XOR3 against XOR3=fnOf(XOR2) , it's NAND gate:
again we have the 2N5087 - used inplace of russian МП42Б germanium 1 - based design drawing in average 9µA/stg.
and the slowest exception drawing in average 1.87µA/stg.
the 2N5087 based
the primary objective of this research was to find optimum way to utilize some old transistors as misc. LE 1.2V logic gates
we made some findings on this subj. but it still remains far from being researched
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