Sunday, January 1, 2017

component level model for C-MOS inverter

Revised the R.DS.ON data for C-MOS inverters

thought to complete the set by scanning the threshold levels
1-st came out with an over complicated setup -- that however worked fine at least for 3-shold meter circuit

analysing the problem revealed the alternate more simple 3-shld. metering possibilities -- however i can't tell witch of those is more reliable - as by simply measuring the current through opening FET gives us lower 3-shld. points than any of these metering grids . . .

so shit - started from the middle using approximate initial values and tuned the CLM (component level model) on a run . . .

i had previously done some measurements that suited the purpose - of tuning the CLM

the apx. src. fn. for the prev. graphs

! note that the SPICE uses "randomly" RAD-s and DEG-s (as why to make life easier by using phs. std. radians -- as it is a scientific application ? - perhaps another computer game ....)

the ↓next↓ is how we got to ↑above↑

confirming/testing/simulating a threshold metering variant

it seems i should have made the NOT gate to use more power (to be faster) -- &shit -- it'll do for testing as low speed MOS inverter -- so here some test follow :
at your Left -- 5x ring osc. has !usually! enough  delay for digital levels to settle e.g. 5x ring osc. generates "square" trapezoid wave while 3x ring osc. does sine or triangle
at your Right -- a "std." digital R-C CLK circuit

at your Left -- synchronizing 5x & 7x ring osc.-s
at your Right -- setting up something resembling to a quadrature osc.

at your Left -- the same "quadrature osc." at lower speed
at your Right -- . . . as the RA is less than RB -- then here we reference the inverter to a digital threshold point and feeding the output of the inverter to inverting threshold reference . . . after "optimizing" this type of oscillator we got the schematic shown on the fig.

at your Left -- some oscillator i came up with before starting to use the Spice simulator (. . . "what's it worth")
at your Right -- another variant of something i used with experimental DTL gates

at your Left -- an experimental X-tal driver -- when it stabilizes there is still some effect from a near square wave output . . . which is not good . . . i assume
at your Right -- more simple v. of an experimental X-tal driver has even worse sq.wave mix-in -- there must be some sort of dynamic attenuation of the feedback as the crystal charges up (at too strong fixed attenuation the crystal won't likely start up at all . . .)


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