Tuesday, August 8, 2017

Misc. "non-std." RS-triggers

derived from the idea of the pulse RS trigger

ALL
BOXES (positioned as above)
 (blah, blah ....) . . . the upper plot on the graph (N,L) , lower right (X4) is the "first attempt" to "Pass Gate" model the function of the TTL v.´s substitute the upper right (X2) however it's actual function is - set the signal by first set input and update as soon as next clear input occurs (e.g. only one of the inputs being high) extra to that the first risen input locks the other one off so it has no effect as long the firsty stays high

. . . the lower plot on the graph (X,W) , upper right (X2) is what was the aim (similar to linked TTL´s substitute at the beginning of the post) -- the function - set the OUTP by the first risen INP , ignore all input until both inputs are pulled down

. . . the 2-nd lower plot is for "Pass Gate" v. of (X2) - the (K,M) graph , upper left (X1) - took a bit tricky "gate" drive logic to get it going the way it should -- the function - same as X2 only with a bit faster responce . . .

. . . the 2-nd upper plot (S,T) , lower left (X3) is as X2 and X1 only the OUTP is set when input is (Zero,Zero) and the output is set by the first risen from (Zero,Zero) - so the trigger here remembers where it should be going and goes there when INP is "clear" . . . (simple as soapy water)

• • •

the initial purpose of the kind of RS mod. was counters study as below (the N,L - X4 - v. won't work with the below v. of D-Latch coz it would continuously see it's inverted output and starts strobing while D-Latch passes data . . .)

+ an extreme v. of the above T-flops with an experimental Pass Gate



[Eop]

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