"Flasher" revisited , DB3 spice programmatic model Test

The inverter v. of LED-Flasher . . . at various dev. stg.-s

The boost converter v. with new voltage reference

the new voltage reference

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the next thing i actually built (*with protective fuse - not in simulation) - WYCIWYG . . . almost

. . . at both modes you mostly perceive the thing "blinking" - only the after-flash at second mode makes it some different from simple blinking . . . donno

! Note : * it is . . . wise to fuse the mains equipment  also as dumb as that coz - such being experimental you never be too careful to predict weld failure either caused by heating components or bad quality weld/materials . . . . . . . . . also when whatever fails and op.-l parameters exceed the intended design values they won't all burn off - extra to that i got the elongation wire with switch - so i can cut it manually every time there's even a slight suspicion something is about to go wrong

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Depletion mode MOSFET - macro model - some essencial tests

about BSS139 -- R_DSON

10MHz - random drive (i donno any specifics about these devices)

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Random Op Amp Voltage References

as it shows -- first required for CC-sink -- next it will be used to adjust 78L05 and further

The above circuits are a modification of double R-Diode input "bridge"

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Next the voltage reference at -- aa dumps it's excess to Op Amp.-s negative input -- bb

Another 2x R~D bridge that seems to have a capability to stand up to frequency variations ?

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Insane

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Positive feedback shunting regulator or custom zener

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testing textbook voltage regulators

the src. A (fig. ⓐ) - won't start up with higher ß , silica "western" transistors

if we add a "startup**" it won't be overload proof -- it is possible to set there a time constant based startup "boost" that charges the output capacitor to near nominal output at no or moderate load connected . . . why all this fuzz - i just studied the circuit for it's simplicity . . .
. . . the next is what i came out as a near reasonable practical solution for the type of regulator (or what's left of that type)

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update: an alternate "startup**" v. that is still overload proof only it requires extra "Discharge" button to get off the "output disabled mode" -- to make it also "user proof" requires a special discharge or power button so that the discharge engages only when external supply can't charge the caps. -- all cool the simlpe things are not simple . . .

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the src. B (the leftmost fig.) -- works good as shown as long the input voltage is higher the output plus NPN-s BE vtg. drop + Op Amp-s incapability to reach positive rail some 1 to 2 V

if we power the regulator control circuitry from separate supplies - we get the foldback v. of the above src.

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component level model for C-MOS inverter

Revised the R.DS.ON data for C-MOS inverters

thought to complete the set by scanning the threshold levels
1-st came out with an over complicated setup -- that however worked fine at least for 3-shold meter circuit

analysing the problem revealed the alternate more simple 3-shld. metering possibilities -- however i can't tell witch of those is more reliable - as by simply measuring the current through opening FET gives us lower 3-shld. points than any of these metering grids . . .

so shit - started from the middle using approximate initial values and tuned the CLM (component level model) on a run . . .

i had previously done some measurements that suited the purpose - of tuning the CLM

the apx. src. fn. for the prev. graphs

! note that the SPICE uses "randomly" RAD-s and DEG-s (as why to make life easier by using phs. std. radians -- as it is a scientific application ? - perhaps another computer game ....)

the ↓next↓ is how we got to ↑above↑

confirming/testing/simulating a threshold metering variant

it seems i should have made the NOT gate to use more power (to be faster) -- &shit -- it'll do for testing as low speed MOS inverter -- so here some test follow :
at your Left -- 5x ring osc. has !usually! enough  delay for digital levels to settle e.g. 5x ring osc. generates "square" trapezoid wave while 3x ring osc. does sine or triangle
at your Right -- a "std." digital R-C CLK circuit

at your Left -- synchronizing 5x & 7x ring osc.-s
at your Right -- setting up something resembling to a quadrature osc.

at your Left -- the same "quadrature osc." at lower speed
at your Right -- . . . as the RA is less than RB -- then here we reference the inverter to a digital threshold point and feeding the output of the inverter to inverting threshold reference . . . after "optimizing" this type of oscillator we got the schematic shown on the fig.

at your Left -- some oscillator i came up with before starting to use the Spice simulator (. . . "what's it worth")
at your Right -- another variant of something i used with experimental DTL gates

at your Left -- an experimental X-tal driver -- when it stabilizes there is still some effect from a near square wave output . . . which is not good . . . i assume
at your Right -- more simple v. of an experimental X-tal driver has even worse sq.wave mix-in -- there must be some sort of dynamic attenuation of the feedback as the crystal charges up (at too strong fixed attenuation the crystal won't likely start up at all . . .)

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